soc: xtensa_sample_controller: Port to HWMv2

Ports the xtensa_sample_controller SoC configuration to hardware
model version 2

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>

soc/v2/cadence/xtensa_sample_controller/Kconfig

@@ -2,7 +2,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_XTENSA_SAMPLE_CONTROLLER
-	bool "Xtensa sample_controller core"
 	select XTENSA
 	select XTENSA_HAL
 	select ARCH_SUPPORTS_COREDUMP

soc/v2/cadence/xtensa_sample_controller/Kconfig.soc

@@ -0,0 +1,12 @@
+# Copyright (c) 2017 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_XTENSA_SAMPLE_CONTROLLER
+	bool
+
+config SOC
+	default "xtensa_sample_controller" if SOC_XTENSA_SAMPLE_CONTROLLER
+
+config SOC_TOOLCHAIN_NAME
+	string
+	default "sample_controller" if SOC_XTENSA_SAMPLE_CONTROLLER

soc/v2/cadence/xtensa_sample_controller/soc.yml

@@ -0,0 +1,4 @@
+series:
+- name: xtensa_sample_controller
+  socs:
+  - name: xtensa_sample_controller

soc/xtensa/sample_controller/Kconfig.defconfig

@@ -1,16 +0,0 @@
-# XTENSA board configuration
-
-# Copyright (c) 2016 Open-RnD Sp. z o.o.
-# Copyright (c) 2016 Cadence Design Systems, Inc.
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_XTENSA_SAMPLE_CONTROLLER
-
-config SOC
-	default "sample_controller"
-
-config SOC_TOOLCHAIN_NAME
-	string
-	default "sample_controller"
-
-endif