78f05163d6
Add driver for the Texas Instruments TLV320AIC3110 audio codec. Signed-off-by: Florijan Plohl <florijan.plohl@norik.com>
301 lines
9.6 KiB
C
301 lines
9.6 KiB
C
/*
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* Copyright (c) 2025 PHYTEC America LLC
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* Author: Florijan Plohl <florijan.plohl@norik.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_AUDIO_TLV320DAC310X_H_
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#define ZEPHYR_DRIVERS_AUDIO_TLV320DAC310X_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Register addresses */
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#define PAGE_CONTROL_ADDR 0
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/* Register addresses {page, address} and fields */
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#define SOFT_RESET_ADDR (struct reg_addr){0, 1}
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#define SOFT_RESET_ASSERT (1)
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#define CLOCK_GEN_MUX_ADDR (struct reg_addr){0, 4}
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#define CLOCK_GEN_MUX_DEFAULT (0x3)
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#define PLL_P_R_ADDR (struct reg_addr){0, 5}
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#define PLL_POWER_UP BIT(7)
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#define PLL_POWER_UP_MASK BIT(7)
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#define PLL_P_MASK BIT_MASK(3)
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#define PLL_P(val) (((val) & PLL_P_MASK) << 4)
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#define PLL_R_MASK BIT_MASK(4)
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#define PLL_R(val) ((val) & PLL_R_MASK)
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#define PLL_J_ADDR (struct reg_addr){0, 6}
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#define PLL_D_MSB_ADDR (struct reg_addr){0, 7}
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#define PLL_D_LSB_ADDR (struct reg_addr){0, 8}
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#define NDAC_DIV_ADDR (struct reg_addr){0, 11}
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#define NDAC_POWER_UP BIT(7)
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#define NDAC_POWER_UP_MASK BIT(7)
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#define NDAC_DIV_MASK BIT_MASK(7)
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#define NDAC_DIV(val) ((val) & NDAC_DIV_MASK)
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#define MDAC_DIV_ADDR (struct reg_addr){0, 12}
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#define MDAC_POWER_UP BIT(7)
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#define MDAC_POWER_UP_MASK BIT(7)
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#define MDAC_DIV_MASK BIT_MASK(7)
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#define MDAC_DIV(val) ((val) & MDAC_DIV_MASK)
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#define OSR_MSB_ADDR (struct reg_addr){0, 13}
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#define OSR_MSB_MASK BIT_MASK(2)
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#define OSR_LSB_ADDR (struct reg_addr){0, 14}
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#define OSR_LSB_MASK BIT_MASK(8)
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#define NADC_DIV_ADDR (struct reg_addr){0, 18}
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#define NADC_POWER_UP BIT(7)
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#define NADC_POWER_UP_MASK BIT(7)
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#define NADC_DIV_MASK BIT_MASK(7)
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#define NADC_DIV(val) ((val) & NADC_DIV_MASK)
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#define MADC_DIV_ADDR (struct reg_addr){0, 19}
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#define MADC_POWER_UP BIT(7)
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#define MADC_POWER_UP_MASK BIT(7)
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#define MADC_DIV_MASK BIT_MASK(7)
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#define MADC_DIV(val) ((val) & MADC_DIV_MASK)
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#define AOSR_ADDR (struct reg_addr){0, 20}
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#define IF_CTRL1_ADDR (struct reg_addr){0, 27}
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#define IF_CTRL_IFTYPE_MASK BIT_MASK(1)
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#define IF_CTRL_IFTYPE_I2S 0
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#define IF_CTRL_IFTYPE_DSP 1
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#define IF_CTRL_IFTYPE_RJF 2
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#define IF_CTRL_IFTYPE_LJF 3
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#define IF_CTRL_IFTYPE(val) (((val) & IF_CTRL_IFTYPE_MASK) << 6)
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#define IF_CTRL_WLEN_MASK BIT_MASK(2)
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#define IF_CTRL_WLEN(val) (((val) & IF_CTRL_WLEN_MASK) << 4)
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#define IF_CTRL_WLEN_16 0
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#define IF_CTRL_WLEN_20 1
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#define IF_CTRL_WLEN_24 2
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#define IF_CTRL_WLEN_32 3
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#define IF_CTRL_BCLK_OUT BIT(3)
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#define IF_CTRL_WCLK_OUT BIT(2)
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#define IF_CTRL_DOUT_HIGH_Z BIT(0)
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#define BCLK_DIV_ADDR (struct reg_addr){0, 30}
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#define BCLK_DIV_POWER_UP BIT(7)
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#define BCLK_DIV_POWER_UP_MASK BIT(7)
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#define BCLK_DIV_MASK BIT_MASK(7)
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#define BCLK_DIV(val) ((val) & MDAC_DIV_MASK)
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#define OVF_FLAG_ADDR (struct reg_addr){0, 39}
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#define DAC_PROC_BLK_SEL_ADDR (struct reg_addr){0, 60}
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#define DAC_PROC_BLK_SEL_MASK BIT_MASK(5)
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#define DAC_PROC_BLK_SEL(val) ((val) & DAC_PROC_BLK_SEL_MASK)
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#define ADC_PROC_BLK_SEL_ADDR (struct reg_addr){0, 61}
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#define ADC_PROC_BLK_SEL_MASK BIT_MASK(5)
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#define ADC_PROC_BLK_SEL(val) ((val) & ADC_PROC_BLK_SEL_MASK)
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#define DATA_PATH_SETUP_ADDR (struct reg_addr){0, 63}
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#define DAC_LR_POWERUP_DEFAULT (BIT(7) | BIT(6) | BIT(4) | BIT(2))
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#define DAC_LR_POWERDN_DEFAULT (BIT(4) | BIT(2))
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#define VOL_CTRL_ADDR (struct reg_addr){0, 64}
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#define VOL_CTRL_UNMUTE_DEFAULT (0)
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#define VOL_CTRL_MUTE_DEFAULT (BIT(3) | BIT(2))
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#define L_DIG_VOL_CTRL_ADDR (struct reg_addr){0, 65}
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#define DRC_CTRL1_ADDR (struct reg_addr){0, 68}
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#define L_BEEP_GEN_ADDR (struct reg_addr){0, 71}
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#define BEEP_GEN_EN_BEEP (BIT(7))
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#define R_BEEP_GEN_ADDR (struct reg_addr){0, 72}
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#define BEEP_LEN_MSB_ADDR (struct reg_addr){0, 73}
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#define BEEP_LEN_MIB_ADDR (struct reg_addr){0, 74}
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#define BEEP_LEN_LSB_ADDR (struct reg_addr){0, 75}
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/* Page 1 registers */
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/* Headphone driver registers */
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#define HEADPHONE_DRV_ADDR (struct reg_addr){1, 31}
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#define HEADPHONE_DRV_POWERUP (BIT(7) | BIT(6))
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#define HEADPHONE_DRV_CM_MASK (BIT_MASK(2) << 3)
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#define HEADPHONE_DRV_CM(val) (((val) << 3) & HEADPHONE_DRV_CM_MASK)
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#define HEADPHONE_DRV_RESERVED (BIT(2))
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#define HP_OUT_POP_RM_ADDR (struct reg_addr){1, 33}
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#define HP_OUT_POP_RM_ENABLE (BIT(7))
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#define OUTPUT_ROUTING_ADDR (struct reg_addr){1, 35}
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#define OUTPUT_ROUTING_HPL BIT(7)
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#define OUTPUT_ROUTING_HPR BIT(3)
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#define HPL_ANA_VOL_CTRL_ADDR (struct reg_addr){1, 36}
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#define HPR_ANA_VOL_CTRL_ADDR (struct reg_addr){1, 37}
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#define HPX_ANA_VOL_ENABLE BIT(7)
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#define HPX_ANA_VOL_MASK BIT_MASK(7)
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#define HPX_ANA_VOL(val) (((val) & HPX_ANA_VOL_MASK) | \
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HPX_ANA_VOL_ENABLE)
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#define HPX_ANA_VOL_MAX (0)
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#define HPX_ANA_VOL_DEFAULT (0)
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#define HPX_ANA_VOL_MIN (127)
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#define HPX_ANA_VOL_MUTE (HPX_ANA_VOL_MIN | ~HPX_ANA_VOL_ENABLE)
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#define HPX_ANA_VOL_LOW_THRESH (105)
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#define HPX_ANA_VOL_FLOOR (144)
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#define HPL_DRV_GAIN_CTRL_ADDR (struct reg_addr){1, 40}
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#define HPR_DRV_GAIN_CTRL_ADDR (struct reg_addr){1, 41}
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#define HPX_DRV_UNMUTE (BIT(2))
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#define HPX_DRV_RESERVED (BIT(1)) /* Write only 1 */
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#define HEADPHONE_DRV_CTRL_ADDR (struct reg_addr){1, 44}
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#define HEADPHONE_DRV_LINEOUT (BIT(1) | BIT(2))
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/* Class-D speaker amplifier registers */
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#define SPEAKER_DRV_ADDR (struct reg_addr){1, 32}
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#define SPEAKER_DRV_POWERUP BIT(7) | BIT(6)
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#define SPEAKER_DRV_RESERVED BIT(2) | BIT(1)
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#define OUTPUT_ROUTING_MIXER BIT(6) | BIT(2)
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#define SPL_ANA_VOL_CTRL_ADDR (struct reg_addr){1, 38}
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#define SPR_ANA_VOL_CTRL_ADDR (struct reg_addr){1, 39}
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#define SPX_ANA_VOL_ENABLE BIT(7)
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#define SPX_ANA_VOL_MASK (BIT_MASK(7))
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#define SPX_ANA_VOL(val) (((val) & SPX_ANA_VOL_MASK) | \
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SPX_ANA_VOL_ENABLE)
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#define SPX_ANA_VOL_MAX (0)
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#define SPX_ANA_VOL_DEFAULT (0)
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#define SPX_ANA_VOL_MIN (127)
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#define SPX_ANA_VOL_MUTE (SPX_ANA_VOL_MIN | ~SPX_ANA_VOL_ENABLE)
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#define SPX_ANA_VOL_LOW_THRESH (105)
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#define SPX_ANA_VOL_FLOOR (144)
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#define SPL_DRV_GAIN_CTRL_ADDR (struct reg_addr){1, 42}
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#define SPR_DRV_GAIN_CTRL_ADDR (struct reg_addr){1, 43}
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#define SPX_DRV_UNMUTE (BIT(2))
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#define SPX_DRV_RESERVED (BIT(1)) /* Write only 0 */
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/* ADC Mic registers */
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#define MIC_ADC_CTRL_ADDR (struct reg_addr){0, 81}
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#define MIC_ADC_POWERUP BIT(7)
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#define MIC_ADC_FLAG_ADDR (struct reg_addr){0, 36}
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#define MIC_FCTRL_ADDR (struct reg_addr){0, 82}
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#define MIC_FCTRL_DEFAULT 0x0
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#define MIC_CCTRL_ADDR (struct reg_addr){0, 83}
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#define MIC_CCTRL_DEFAULT 0x0
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#define MIC_BIAS_ADDR (struct reg_addr){1, 46}
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#define MICBIAS_DEFAULT (BIT(3) | BIT(1))
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#define MIC_PGA_ADDR (struct reg_addr){1, 47} /* Missing in datasheet */
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#define MIC_PGA_VOL_DEFAULT 0x0 /* 0.5 dB/bit, max volume: 59.5 dB */
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#define MIC_PGAPI_ADDR (struct reg_addr){1, 48}
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#define MIC_PGAPI_L_DEFAULT (BIT(7) | BIT(6))
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#define MIC_PGAPI_R_DEFAULT (BIT(5) | BIT(4))
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#define MIC_PGAMI_ADDR (struct reg_addr){1, 49}
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#define MIC_ICM_ADDR (struct reg_addr){1, 50}
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/* Page 3 registers */
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#define TIMER_MCLK_DIV_ADDR (struct reg_addr){3, 16}
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#define TIMER_MCLK_DIV_EN_EXT (BIT(7))
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#define TIMER_MCLK_DIV_MASK (BIT_MASK(7))
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#define TIMER_MCLK_DIV_VAL(val) ((val) & TIMER_MCLK_DIV_MASK)
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struct reg_addr {
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uint8_t page; /* page number */
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uint8_t reg_addr; /* register address */
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};
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enum dac_proc_block {
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PRB_P1_DECIMATION_A = 1,
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PRB_P7_DECIMATION_B = 7,
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PRB_P17_DECIMATION_C = 17,
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};
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enum adc_proc_block {
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PRB_R4_DECIMATION_A = 4,
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PRB_R10_DECIMATION_B = 10,
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PRB_R16_DECIMATION_C = 16,
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};
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enum cm_voltage {
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CM_VOLTAGE_1P35 = 0,
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CM_VOLTAGE_1P5 = 1,
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CM_VOLTAGE_1P65 = 2,
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CM_VOLTAGE_1P8 = 3,
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};
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struct tlv320aic3110_rate_divs {
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uint32_t mclk;
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uint32_t rate;
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uint8_t pll_p;
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uint8_t pll_j;
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uint16_t pll_d;
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uint8_t dosr;
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uint8_t ndac;
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uint8_t mdac;
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uint8_t aosr;
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uint8_t nadc;
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uint8_t madc;
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};
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/* PLL configurations */
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static const struct tlv320aic3110_rate_divs pll_div_table[] = {
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/* mclk rate pll: p j d dosr ndac mdac aors nadc madc */
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/* 8k rate */
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{12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2},
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{24000000, 8000, 2, 8, 1920, 128, 48, 2, 128, 48, 2},
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{25000000, 8000, 2, 7, 8643, 128, 48, 2, 128, 48, 2},
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/* 11.025k rate */
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{12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2},
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{24000000, 11025, 2, 7, 5264, 128, 32, 2, 128, 32, 2},
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{25000000, 11025, 2, 7, 2253, 128, 32, 2, 128, 32, 2},
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/* 16k rate */
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{12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2},
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{24000000, 16000, 2, 8, 1920, 128, 24, 2, 128, 24, 2},
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{25000000, 16000, 2, 7, 8643, 128, 24, 2, 128, 24, 2},
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/* 22.05k rate */
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{12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2},
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{24000000, 22050, 2, 7, 5264, 128, 16, 2, 128, 16, 2},
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{25000000, 22050, 2, 7, 2253, 128, 16, 2, 128, 16, 2},
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/* 32k rate */
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{12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2},
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{24000000, 32000, 2, 8, 1920, 128, 12, 2, 128, 12, 2},
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{25000000, 32000, 2, 7, 8643, 128, 12, 2, 128, 12, 2},
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/* 44.1k rate */
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{12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2},
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{24000000, 44100, 2, 7, 5264, 128, 8, 2, 128, 8, 2},
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{25000000, 44100, 2, 7, 2253, 128, 8, 2, 128, 8, 2},
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/* 48k rate */
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{12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2},
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{24000000, 48000, 2, 8, 1920, 128, 8, 2, 128, 8, 2},
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{25000000, 48000, 2, 7, 8643, 128, 8, 2, 128, 8, 2},
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/* 88.2k rate */
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{12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2},
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{24000000, 88200, 2, 7, 5264, 64, 8, 2, 64, 8, 2},
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{25000000, 88200, 2, 7, 2253, 64, 8, 2, 64, 8, 2},
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/* 96k rate */
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{12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2},
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{24000000, 96000, 2, 8, 1920, 64, 8, 2, 64, 8, 2},
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{25000000, 96000, 2, 7, 8643, 64, 8, 2, 64, 8, 2},
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/* 176.4k rate */
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{12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2},
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{24000000, 176400, 2, 7, 5264, 32, 8, 2, 32, 8, 2},
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{25000000, 176400, 2, 7, 2253, 32, 8, 2, 32, 8, 2},
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/* 192k rate */
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{12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2},
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{24000000, 192000, 2, 8, 1920, 32, 8, 2, 32, 8, 2},
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{25000000, 192000, 2, 7, 8643, 32, 8, 2, 32, 8, 2},
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};
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_DRIVERS_AUDIO_TLV320DAC310X_H_ */
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