b13d9a0510
The format currently expected by devices and sample display
application for BGR_565 is actually RGB_565 format with bytes
swapped (not B / R swapped). That is:
PIXEL_FORMAT_RGB_565:
* @code{.unparsed}
* 7......0 15.....8
* | gggBbbbb RrrrrGgg | ...
* @endcode
current PIXEL_FORMAT_BGR_565:
* @code{.unparsed}
* 7......0 15.....8
* | RrrrrGgg gggBbbbb | ...
* @endcode
This is explained in both st7796s display driver but also is
what is generated by the sample display application. As a video
format (ex: V4L2), such format is not mentioned as BGR (for
which R and B are swapped) but RGB_565X.
Within the whole Zephyr tree, rename the curremt BGR_565 format
into RGB_565X in order to emphasis that this is a byte swapped
format rather than a B/G component swapped format.
This also correct the description of the format in display.h
file, which wasn't correct based on what was being used by
display driver or sample display app.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
374 lines
16 KiB
C
374 lines
16 KiB
C
/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_lcdifv3
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#include <zephyr/drivers/display.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/kernel.h>
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#include <fsl_lcdifv3.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/irq.h>
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#include <zephyr/cache.h>
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LOG_MODULE_REGISTER(display_mcux_lcdifv3, CONFIG_DISPLAY_LOG_LEVEL);
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/* Required by DEVICE_MMIO_NAMED_* macros */
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#define DEV_CFG(_dev) ((const struct mcux_lcdifv3_config *)(_dev)->config)
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#define DEV_DATA(_dev) ((struct mcux_lcdifv3_data *)(_dev)->data)
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struct mcux_lcdifv3_config {
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DEVICE_MMIO_NAMED_ROM(reg_base);
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const struct device *disp_pix_clk_dev;
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clock_control_subsys_t disp_pix_clk_subsys;
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uint32_t disp_pix_clk_rate;
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const struct device *media_axi_clk_dev;
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clock_control_subsys_t media_axi_clk_subsys;
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uint32_t media_axi_clk_rate;
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const struct device *media_apb_clk_dev;
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clock_control_subsys_t media_apb_clk_subsys;
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uint32_t media_apb_clk_rate;
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void (*irq_config_func)(const struct device *dev);
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lcdifv3_buffer_config_t buffer_config;
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lcdifv3_display_config_t display_config;
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enum display_pixel_format pixel_format;
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uint8_t *fb_ptr;
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size_t fb_bytes;
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};
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struct mcux_lcdifv3_data {
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DEVICE_MMIO_NAMED_RAM(reg_base);
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/* Pointer to active framebuffer */
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const uint8_t *active_fb;
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uint8_t *fb[CONFIG_MCUX_LCDIFV3_FB_NUM];
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uint8_t pixel_bytes;
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struct k_sem sem;
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/* Tracks index of next active driver framebuffer */
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uint8_t next_idx;
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};
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static void dump_reg(LCDIF_Type *base)
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{
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/* Dump LCDIF Registers */
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LOG_DBG("CTRL: 0x%x", base->CTRL.RW);
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LOG_DBG("DISP_PARA: 0x%x", base->DISP_PARA);
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LOG_DBG("DISP_SIZE: 0x%x", base->DISP_SIZE);
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LOG_DBG("HSYN_PARA: 0x%x", base->HSYN_PARA);
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LOG_DBG("VSYN_PARA: 0x%x", base->VSYN_PARA);
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LOG_DBG("VSYN_HSYN_WIDTH: 0x%x", base->VSYN_HSYN_WIDTH);
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LOG_DBG("INT_STATUS_D0: 0x%x", base->INT_STATUS_D0);
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LOG_DBG("INT_STATUS_D1: 0x%x", base->INT_STATUS_D1);
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LOG_DBG("CTRLDESCL_1: 0x%x", base->CTRLDESCL_1[0]);
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LOG_DBG("CTRLDESCL_3: 0x%x", base->CTRLDESCL_3[0]);
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LOG_DBG("CTRLDESCL_LOW_4: 0x%x", base->CTRLDESCL_LOW_4[0]);
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LOG_DBG("CTRLDESCL_HIGH_4: 0x%x", base->CTRLDESCL_HIGH_4[0]);
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LOG_DBG("CTRLDESCL_5: 0x%x", base->CTRLDESCL_5[0]);
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}
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static int mcux_lcdifv3_write(const struct device *dev, const uint16_t x, const uint16_t y,
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const struct display_buffer_descriptor *desc, const void *buf)
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{
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const struct mcux_lcdifv3_config *config = dev->config;
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struct mcux_lcdifv3_data *data = dev->data;
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LCDIF_Type *base = (LCDIF_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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uint32_t h_idx;
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const uint8_t *src;
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uint8_t *dst;
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__ASSERT((data->pixel_bytes * desc->pitch * desc->height) <= desc->buf_size,
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"Input buffer too small");
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LOG_DBG("W=%d, H=%d @%d,%d", desc->width, desc->height, x, y);
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if ((x == 0) && (y == 0) && (desc->width == config->display_config.panelWidth) &&
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(desc->height == config->display_config.panelHeight) && (desc->pitch == desc->width)) {
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/* We can use the display buffer directly, without copying */
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LOG_DBG("Setting FB from %p->%p", (void *)data->active_fb, (void *)buf);
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data->active_fb = buf;
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} else {
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/* We must use partial framebuffer copy */
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if (CONFIG_MCUX_LCDIFV3_FB_NUM == 0) {
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LOG_ERR("Partial display refresh requires driver framebuffers");
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return -ENOTSUP;
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} else if (data->active_fb != data->fb[data->next_idx]) {
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/*
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* Copy the entirety of the current framebuffer to new
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* buffer, since we are changing the active buffer address
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*/
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src = data->active_fb;
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dst = data->fb[data->next_idx];
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memcpy(dst, src, config->fb_bytes);
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}
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/* Write the display update to the active framebuffer */
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src = buf;
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dst = data->fb[data->next_idx];
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dst += data->pixel_bytes * (y * config->display_config.panelWidth + x);
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for (h_idx = 0; h_idx < desc->height; h_idx++) {
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memcpy(dst, src, data->pixel_bytes * desc->width);
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src += data->pixel_bytes * desc->pitch;
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dst += data->pixel_bytes * config->display_config.panelWidth;
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}
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LOG_DBG("Setting FB from %p->%p", (void *)data->active_fb,
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(void *)data->fb[data->next_idx]);
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/* Set new active framebuffer */
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data->active_fb = data->fb[data->next_idx];
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}
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sys_cache_data_flush_and_invd_range((void *)data->active_fb, config->fb_bytes);
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k_sem_reset(&data->sem);
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/* Set new framebuffer */
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LCDIFV3_SetLayerBufferAddr(base, 0, (uint32_t)(uintptr_t)data->active_fb);
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LCDIFV3_TriggerLayerShadowLoad(base, 0);
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#if CONFIG_MCUX_LCDIFV3_FB_NUM != 0
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/* Update index of active framebuffer */
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data->next_idx = (data->next_idx + 1) % CONFIG_MCUX_LCDIFV3_FB_NUM;
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#endif
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/* Wait for frame to complete */
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k_sem_take(&data->sem, K_FOREVER);
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return 0;
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}
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static void *mcux_lcdifv3_get_framebuffer(const struct device *dev)
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{
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struct mcux_lcdifv3_data *dev_data = dev->data;
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return (void *)dev_data->active_fb;
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}
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static void mcux_lcdifv3_get_capabilities(const struct device *dev,
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struct display_capabilities *capabilities)
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{
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const struct mcux_lcdifv3_config *config = dev->config;
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memset(capabilities, 0, sizeof(struct display_capabilities));
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capabilities->x_resolution = config->display_config.panelWidth;
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capabilities->y_resolution = config->display_config.panelHeight;
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capabilities->supported_pixel_formats = config->pixel_format;
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capabilities->current_pixel_format = config->pixel_format;
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capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL;
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}
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static void mcux_lcdifv3_isr(const struct device *dev)
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{
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struct mcux_lcdifv3_data *dev_data = dev->data;
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uint32_t status;
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LCDIF_Type *base = (LCDIF_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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status = LCDIFV3_GetInterruptStatus(base);
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LCDIFV3_ClearInterruptStatus(base, status);
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k_sem_give(&dev_data->sem);
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}
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static int mcux_lcdifv3_configure_clock(const struct device *dev)
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{
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const struct mcux_lcdifv3_config *config = dev->config;
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clock_control_set_rate(config->disp_pix_clk_dev, config->disp_pix_clk_subsys,
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(clock_control_subsys_rate_t)(uintptr_t)config->disp_pix_clk_rate);
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return 0;
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}
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static int mcux_axi_apb_configure_clock(const struct device *dev)
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{
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const struct mcux_lcdifv3_config *config = dev->config;
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uint32_t clk_freq;
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/* configure media_axi_clk */
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if (!device_is_ready(config->media_axi_clk_dev)) {
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LOG_ERR("media_axi clock control device not ready");
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return -ENODEV;
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}
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clock_control_set_rate(config->media_axi_clk_dev, config->media_axi_clk_subsys,
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(clock_control_subsys_rate_t)(uintptr_t)config->media_axi_clk_rate);
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if (clock_control_get_rate(config->media_axi_clk_dev, config->media_axi_clk_subsys,
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&clk_freq)) {
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return -EINVAL;
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}
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LOG_DBG("media_axi clock frequency %d", clk_freq);
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/* configure media_apb_clk */
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if (!device_is_ready(config->media_apb_clk_dev)) {
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LOG_ERR("media_apb clock control device not ready");
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return -ENODEV;
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}
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clock_control_set_rate(config->media_apb_clk_dev, config->media_apb_clk_subsys,
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(clock_control_subsys_rate_t)(uintptr_t)config->media_apb_clk_rate);
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if (clock_control_get_rate(config->media_apb_clk_dev, config->media_apb_clk_subsys,
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&clk_freq)) {
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return -EINVAL;
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}
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LOG_DBG("media_apb clock frequency %d", clk_freq);
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return 0;
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}
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static int mcux_lcdifv3_init(const struct device *dev)
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{
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const struct mcux_lcdifv3_config *config = dev->config;
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struct mcux_lcdifv3_data *data = dev->data;
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uint32_t clk_freq;
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DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP);
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LCDIF_Type *base = (LCDIF_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
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config->irq_config_func(dev);
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for (int i = 0; i < CONFIG_MCUX_LCDIFV3_FB_NUM; i++) {
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/* Record pointers to each driver framebuffer */
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data->fb[i] = config->fb_ptr + (config->fb_bytes * i);
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}
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data->active_fb = config->fb_ptr;
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k_sem_init(&data->sem, 1, 1);
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/* Clear external memory, as it is uninitialized */
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memset(config->fb_ptr, 0, config->fb_bytes * CONFIG_MCUX_LCDIFV3_FB_NUM);
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/* configure disp_pix_clk */
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if (!device_is_ready(config->disp_pix_clk_dev)) {
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LOG_ERR("cam_pix clock control device not ready");
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return -ENODEV;
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}
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mcux_axi_apb_configure_clock(dev);
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mcux_lcdifv3_configure_clock(dev);
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if (clock_control_get_rate(config->disp_pix_clk_dev, config->disp_pix_clk_subsys,
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&clk_freq)) {
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LOG_ERR("Failed to get disp_pix_clk");
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return -EINVAL;
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}
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LOG_INF("disp_pix clock frequency %d", clk_freq);
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lcdifv3_buffer_config_t buffer_config = config->buffer_config;
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lcdifv3_display_config_t display_config = config->display_config;
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/* Set the Pixel format */
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if (config->pixel_format == PIXEL_FORMAT_RGB_565X) {
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buffer_config.pixelFormat = kLCDIFV3_PixelFormatRGB565;
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} else if (config->pixel_format == PIXEL_FORMAT_RGB_888) {
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buffer_config.pixelFormat = kLCDIFV3_PixelFormatRGB888;
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} else if (config->pixel_format == PIXEL_FORMAT_ARGB_8888) {
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buffer_config.pixelFormat = kLCDIFV3_PixelFormatARGB8888;
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}
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LCDIFV3_Init(base);
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LCDIFV3_SetDisplayConfig(base, &display_config);
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LCDIFV3_EnableDisplay(base, true);
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LCDIFV3_SetLayerBufferConfig(base, 0, &buffer_config);
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LCDIFV3_SetLayerSize(base, 0, display_config.panelWidth, display_config.panelHeight);
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LCDIFV3_EnableLayer(base, 0, true);
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LCDIFV3_EnablePlanePanic(base);
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LCDIFV3_SetLayerBufferAddr(base, 0, (uint64_t)data->fb[0]);
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LCDIFV3_TriggerLayerShadowLoad(base, 0);
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LCDIFV3_EnableInterrupts(base, kLCDIFV3_VerticalBlankingInterrupt);
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LOG_INF("%s init succeeded", dev->name);
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dump_reg(base);
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return 0;
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}
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static const struct display_driver_api mcux_lcdifv3_api = {
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.write = mcux_lcdifv3_write,
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.get_framebuffer = mcux_lcdifv3_get_framebuffer,
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.get_capabilities = mcux_lcdifv3_get_capabilities,
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};
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#define GET_PIXEL_FORMAT(id) \
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((DT_INST_ENUM_IDX(id, pixel_format) == 0) \
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? PIXEL_FORMAT_RGB_565X \
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: ((DT_INST_ENUM_IDX(id, pixel_format) == 1) ? PIXEL_FORMAT_RGB_888 \
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: PIXEL_FORMAT_ARGB_8888))
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#define GET_PIXEL_BYTES(id) \
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((DT_INST_ENUM_IDX(id, pixel_format) == 0) \
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? 2 \
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: ((DT_INST_ENUM_IDX(id, pixel_format) == 1) ? 3 : 4))
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#define MCUX_LCDIFV3_FRAMEBUFFER_DECL(id) \
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uint8_t __aligned(64) \
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mcux_lcdifv3_frame_buffer_##id[DT_INST_PROP(id, width) * DT_INST_PROP(id, height) * \
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GET_PIXEL_BYTES(id) * CONFIG_MCUX_LCDIFV3_FB_NUM]
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#define MCUX_LCDIFV3_FRAMEBUFFER(id) mcux_lcdifv3_frame_buffer_##id
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#define MCUX_LCDIFV3_DEVICE_INIT(id) \
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static void mcux_lcdifv3_config_func_##id(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(id), DT_INST_IRQ(id, priority), mcux_lcdifv3_isr, \
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DEVICE_DT_INST_GET(id), 0); \
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irq_enable(DT_INST_IRQN(id)); \
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} \
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MCUX_LCDIFV3_FRAMEBUFFER_DECL(id); \
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static struct mcux_lcdifv3_data mcux_lcdifv3_data_##id = { \
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.next_idx = 0, \
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.pixel_bytes = GET_PIXEL_BYTES(id), \
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}; \
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static const struct mcux_lcdifv3_config mcux_lcdifv3_config_##id = { \
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DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(id)), \
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.disp_pix_clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_IDX(id, 0)), \
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.disp_pix_clk_subsys = \
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(clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_IDX(id, 0, name), \
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.disp_pix_clk_rate = DT_PROP(DT_INST_CHILD(id, display_timings), clock_frequency), \
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.media_axi_clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_IDX(id, 1)), \
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.media_axi_clk_subsys = \
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(clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_IDX(id, 1, name), \
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.media_axi_clk_rate = DT_INST_PROP(id, media_axi_clk_rate), \
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.media_apb_clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_IDX(id, 2)), \
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.media_apb_clk_subsys = \
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(clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_IDX(id, 2, name), \
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.media_apb_clk_rate = DT_INST_PROP(id, media_apb_clk_rate), \
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.irq_config_func = mcux_lcdifv3_config_func_##id, \
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.buffer_config = \
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{ \
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.strideBytes = GET_PIXEL_BYTES(id) * DT_INST_PROP(id, width), \
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}, \
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.display_config = \
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{ \
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.panelWidth = DT_INST_PROP(id, width), \
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.panelHeight = DT_INST_PROP(id, height), \
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.lineOrder = kLCDIFV3_LineOrderRGBOrYUV, \
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.hsw = DT_PROP(DT_INST_CHILD(id, display_timings), hsync_len), \
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.hfp = DT_PROP(DT_INST_CHILD(id, display_timings), hfront_porch), \
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.hbp = DT_PROP(DT_INST_CHILD(id, display_timings), hback_porch), \
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.vsw = DT_PROP(DT_INST_CHILD(id, display_timings), vsync_len), \
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.vfp = DT_PROP(DT_INST_CHILD(id, display_timings), vfront_porch), \
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.vbp = DT_PROP(DT_INST_CHILD(id, display_timings), vback_porch), \
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.polarityFlags = \
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(DT_PROP(DT_INST_CHILD(id, display_timings), hsync_active) \
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? kLCDIFV3_HsyncActiveLow \
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: kLCDIFV3_HsyncActiveHigh) | \
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(DT_PROP(DT_INST_CHILD(id, display_timings), vsync_active) \
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? kLCDIFV3_VsyncActiveLow \
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: kLCDIFV3_VsyncActiveHigh) | \
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(DT_PROP(DT_INST_CHILD(id, display_timings), de_active) \
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? kLCDIFV3_DataEnableActiveLow \
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: kLCDIFV3_DataEnableActiveHigh) | \
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(DT_PROP(DT_INST_CHILD(id, display_timings), \
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pixelclk_active) \
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? kLCDIFV3_DriveDataOnRisingClkEdge \
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: kLCDIFV3_DriveDataOnFallingClkEdge), \
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}, \
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.pixel_format = GET_PIXEL_FORMAT(id), \
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.fb_ptr = MCUX_LCDIFV3_FRAMEBUFFER(id), \
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.fb_bytes = \
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DT_INST_PROP(id, width) * DT_INST_PROP(id, height) * GET_PIXEL_BYTES(id), \
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}; \
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DEVICE_DT_INST_DEFINE(id, &mcux_lcdifv3_init, NULL, &mcux_lcdifv3_data_##id, \
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&mcux_lcdifv3_config_##id, POST_KERNEL, \
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CONFIG_DISPLAY_INIT_PRIORITY, &mcux_lcdifv3_api);
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DT_INST_FOREACH_STATUS_OKAY(MCUX_LCDIFV3_DEVICE_INIT)
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