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zephyr/drivers/espi/Kconfig.npcx
Tom Chang ab7a558f19 drivers: espi: npcx: workaround for missed IRQ1/12 on NPCX9M7FB 
When the firmware wrote data to KBC/AUX output buffer, the hardware
automatically generated IRQ1/12 to notify the host. After the host read
the data, the EC received an output buffer empty (OBE) interrupt to
indicate that the next byte could be written. However, on the NPCX9M7FB,
this mechanism may cause IRQ1/12 to be missed if the firmware write new
data immediately after detecting that the output buffer is empty,
resulting in incorrect behavior.
To avoid missing IRQ1/12, the flow is changed so that it first checks
VWIRE_AVAIL to ensure no pending VW events. If no VW event is pending,
the firmware writes data to the output buffer and explicitly asserts
IRQ1/12 to notify the host. After the host reads the data and the OBE
interrupt triggers, the firmware clears IRQ1/12.
This updated sequence prevents IRQ1/12 from being lost and ensure
correct notification behavior.

Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
2025-12-08 15:01:15 -05:00

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# NPCX eSPI driver configuration options
# Copyright (c) 2020 Nuvoton Technology Corporation.
# SPDX-License-Identifier: Apache-2.0
config ESPI_NPCX
bool "Nuvoton NPCX embedded controller (EC) ESPI driver"
default y
depends on SOC_FAMILY_NPCX
depends on DT_HAS_NUVOTON_NPCX_ESPI_ENABLED
select PINCTRL
help
This option enables the Intel Enhanced Serial Peripheral Interface
(eSPI) for NPCX family of processors.
config ESPI_NPCX_NPCXN_V1
bool "Nuvoton NPCX ESPI version 1 support"
default y
depends on $(dt_compat_any_has_prop,$(DT_COMPAT_NUVOTON_NPCX_ESPI),support-npcxn-v1,True)
help
This option enables ESPI version 1 support for npcxn variant.
config ESPI_NPCX_NPCXN_V2
bool "Nuvoton NPCX ESPI version 2 support"
default y
depends on $(dt_compat_any_has_prop,$(DT_COMPAT_NUVOTON_NPCX_ESPI),support-npcxn-v2,True)
help
This option enables ESPI version 2 support for npcxn variant.
config ESPI_NPCX_NPCXN_V3
bool "Nuvoton NPCX ESPI version 3 support"
default y
depends on $(dt_compat_any_has_prop,$(DT_COMPAT_NUVOTON_NPCX_ESPI),support-npcxn-v3,True)
help
This option enables ESPI version 3 support for npcxn variant.
config ESPI_NPCX_NPCKN_V1
bool "Nuvoton NPCX ESPI version 1 support"
default y
depends on $(dt_compat_any_has_prop,$(DT_COMPAT_NUVOTON_NPCX_ESPI),support-npckn-v1,True)
help
This option enables ESPI version 1 support for npckn variant.
config ESPI_NPCX_PERIPHERAL_ACPI_SHD_MEM_SIZE
int "Host I/O peripheral port size for shared memory in npcx series"
depends on ESPI_NPCX || ESPI_PERIPHERAL_ACPI_SHM_REGION
default 256
help
This is the port size used by the Host and EC to communicate over
the shared memory region to return the ACPI response data. Please
notice the valid value in npcx ec series for this option is 8/16/32/
64/128/256/512/1024/2048/4096 bytes.
config ESPI_NPCX_PERIPHERAL_HOST_CMD_PARAM_SIZE
int "Host I/O peripheral port size for ec host command in npcx series"
depends on ESPI_NPCX || ESPI_PERIPHERAL_EC_HOST_CMD
default 256
help
This is the port size used by the Host and EC to communicate over
the shared memory region to return the host command parameter data.
Please notice the valid value in npcx ec series for this option is
8/16/32/64/128/256/512/1024/2048/4096 bytes.
config ESPI_NPCX_BYPASS_CH_ENABLE_FATAL_ERROR
bool
depends on ESPI_NPCX_NPCXN_V1 || ESPI_NPCX_NPCXN_V2
default y
help
Workaround the issue documented in NPCX99nF errata rev1_2, No.3.10.
Enabling an eSPI channel during an eSPI transaction might
(with low probability) cause the eSPI_SIF module to transition to
a wrong state and therefore response with FATAL_ERROR on an incoming
transaction.
config ESPI_NPCX_PERIPHERAL_DEBUG_PORT_80_MULTI_BYTE
bool "Host can write 1/2/4 bytes of Port80 data in a eSPI transaction"
depends on (ESPI_NPCX_NPCXN_V2 || ESPI_NPCX_NPCXN_V3) && ESPI_PERIPHERAL_DEBUG_PORT_80
select RING_BUFFER
help
EC can accept 1/2/4 bytes of Port 80 data written from the Host in an
eSPI transaction.
config ESPI_NPCX_PERIPHERAL_DEBUG_PORT_80_RING_BUF_SIZE
int "Debug Port80 ring buffer size"
depends on ESPI_NPCX_PERIPHERAL_DEBUG_PORT_80_MULTI_BYTE
default 256
help
The size of the ring buffer in byte used by the Port80 ISR to store
Postcodes from Host.
config ESPI_NPCX_i8042_KBC_AUX_VWIRE_IRQ_WORKAROUND
bool
default y if SOC_NPCX9M7FB
help
This option enables the workaround to prevent missing IRQ1/IRQ12 when the
firmware writes data to the output buffer immediately after detecting that
the buffer is empty.
config ESPI_NPCX_VWIRE_ENABLE_SEND_CHECK
bool "Check the value was read by host after wire bits changed"
help
This option enables the function to check whether the host has read the value
after the wire data changes.
config ESPI_NPCX_WIRE_SEND_TIMEOUT_US
int "eSPI virtual wire send timeout count"
default 1000
help
The times to check status after sending the eSPI virtual wire signal. The unit
is microseconds (µs).
config ESPI_TAF_NPCX
bool "Nuvoton NPCX embedded controller (EC) ESPI TAF driver"
depends on ESPI_NPCX_NPCXN_V3 || ESPI_NPCX_NPCKN_V1
depends on FLASH
help
This option enables the Intel Enhanced Serial Peripheral Interface
Target Attached Flash (eSPI TAF) for NPCX4/NPCK3 family of processors.
choice ESPI_TAF_ACCESS_MODE_CHOICE
prompt "eSPI TAF Read Access Mode"
default ESPI_TAF_AUTO_MODE
config ESPI_TAF_AUTO_MODE
bool "eSPI TAF Automatic Mode"
help
This is the setting to use auto mode for eSPI TAF read.
config ESPI_TAF_MANUAL_MODE
bool "eSPI TAF Manual Mode"
help
This is the setting to use manual mode for eSPI TAF read.
endchoice
config ESPI_TAF_TX_AVAIL_CHECK_TIME
int "Flash TX Available Check Time (microseconds)"
default 1000000
depends on ESPI_TAF_NPCX
help
This option sets the time interval (in microseconds) for checking
whether the host has sent a GET_FLASH_C command to retrieve the
result.
config ESPI_TAF_PR_NUM
int "Sets of protection region settings"
default 16
help
This size is display how many group of slave attached flash protection
region.
config ESPI_TAF_NPCX_RPMC_SUPPORT
bool "eSPI TAF RPMC support"
depends on ESPI_TAF_NPCX
select FLASH_EX_OP_ENABLED
help
This option enable the handler for eSPI TAF RPMC request.
config ESPI_TAF_NPCX_STS_AWAIT_TIMEOUT
int "A timeout value in microseconds to wait for automatic read status"
depends on ESPI_TAF_NPCX
default 20000
help
This option specifies the timeout value in microseconds (us) for checking
automatic read status.
# The default value 'y' for the existing options if ESPI_NPCX is selected.
if ESPI_NPCX
config ESPI_OOB_CHANNEL
default y
config ESPI_PERIPHERAL_8042_KBC
default y
config ESPI_PERIPHERAL_HOST_IO
default y
config ESPI_PERIPHERAL_DEBUG_PORT_80
default y
config ESPI_PERIPHERAL_EC_HOST_CMD
default y
config ESPI_PERIPHERAL_ACPI_SHM_REGION
default y
config ESPI_PERIPHERAL_CUSTOM_OPCODE
default y
config ESPI_NPCX_SUPP_VW_GPIO
bool "Indicates that the eSPI hardware supports virtual wire GPIOs"
default y if ESPI_NPCX_NPCXN_V2 || ESPI_NPCX_NPCXN_V3
help
Selected if NPCX series supports virtual wire GPIOs in eSPI module.
config ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND
bool
default y if ESPI_NPCX_NPCXN_V3 && ESPI_FLASH_CHANNEL
help
Workaround the issue "Global Reset" in the npcx4 SoC errata.
config ESPI_NPCX_RESET_SLP_SX_VW_ON_ESPI_RST
bool "Reset SLP_Sx virtual wires when eSPI_RST is asserted"
help
The SLP_S3/SLP_S4/SLP_S5/ virtual wires are automatically reset when
eSPI_Reset is asserted on the global reset.
Don't enable this config if the platform implements the Deep-Sx
entry as EC needs to maintain these pins' states per request.
endif #ESPI_NPCX
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