377922dfcf
Initial support for NXP S32K566 M7 & R52: Clock, Pin control, GPIO and Uart Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
33 lines
848 B
Plaintext
33 lines
848 B
Plaintext
# Copyright 2022-2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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config NXP_SIUL2_EIRQ
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bool "NXP SIUL2 external interrupt controller driver"
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default y
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depends on DT_HAS_NXP_SIUL2_EIRQ_ENABLED
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select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
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select PINCTRL
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help
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NXP SIUL2 external interrupt controller driver.
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if NXP_SIUL2_EIRQ
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config NXP_SIUL2_EIRQ_EXT_INTERRUPTS_MAX
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int
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default 8 if SOC_SERIES_S32ZE
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default 16 if SOC_SERIES_S32K5
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default 32 if SOC_SERIES_S32K3 || SOC_SERIES_MCXE31X
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help
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Number of SIUL2 external interrupts per controller. This is a SoC
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integration option.
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config NXP_SIUL2_EIRQ_EXT_INTERRUPTS_GROUP
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int
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default 8
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default 16 if SOC_SERIES_S32K5
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help
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Number of SIUL2 external interrupts grouped into a single core
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interrupt line. This is a SoC integration option.
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endif # NXP_SIUL2_EIRQ
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