6d4900d0b9
Only modify the definitions that need to be changed in the pinmux register; SR/IS will retain their default values after reset. Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
133 lines
3.4 KiB
C
133 lines
3.4 KiB
C
/*
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* Copyright (c) 2025 Core Devices LLC
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* Copyright (c) 2025 SiFli Technologies(Nanjing) Co., Ltd
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sifli_sf32lb52x_pinmux
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#include <zephyr/arch/cpu.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/dt-bindings/pinctrl/sf32lb52x-pinctrl.h>
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#include <zephyr/drivers/clock_control/sf32lb.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/sys/util.h>
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struct sf32lb52x_pinctrl_config {
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uintptr_t pad_sa;
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uintptr_t pad_pa;
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uintptr_t cfg;
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struct sf32lb_clock_dt_spec clock;
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};
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static int pinctrl_configure_pin(pinctrl_soc_pin_t pin)
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{
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const struct device *dev = DEVICE_DT_INST_GET(0);
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const struct sf32lb52x_pinctrl_config *config = dev->config;
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uintptr_t pad;
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uint8_t pinr_offset;
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uint32_t val;
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uint8_t port = FIELD_GET(SF32LB_PORT_MSK, pin);
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uint8_t pad_num = FIELD_GET(SF32LB_PAD_MSK, pin);
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uint8_t ds_idx = FIELD_GET(SF32LB_DS_IDX_MSK, pin);
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uint8_t ds_reg;
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/*
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* PA39-PA42 only have DS1 bit (no DS0), supports only 4mA (DS1=0) or 20mA (DS1=1).
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* - For 2mA/4mA (idx 0,2): use 4mA (DS1=0, reg=0)
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* - For 8mA/12mA (idx 1,3): invalid, return error
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* - For 20mA (idx 4): use 20mA (DS1=1, reg=1)
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* Other pins: 20mA (idx 4) is invalid, ds_idx maps directly to register value.
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*/
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if ((port == SF32LB_PORT_PA) && (pad_num >= 39U) && (pad_num <= 42U)) {
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if (ds_idx == 4U) {
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/* 20mA is valid for PA39-42 */
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ds_reg = 1U;
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} else if ((ds_idx == 0U) || (ds_idx == 2U)) {
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/* 2mA/4mA -> 4mA (DS1=0) */
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ds_reg = 0U;
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} else {
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/* 8mA/12mA not supported on PA39-42 */
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return -EINVAL;
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}
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} else {
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/* Normal pins: 20mA is not valid, ds_idx is the register value */
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if (ds_idx == 4U) {
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return -EINVAL;
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}
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ds_reg = ds_idx;
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}
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/* configure HPSYS_CFG *_PINR if applicable */
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pinr_offset = FIELD_GET(SF32LB_PINR_OFFSET_MSK, pin);
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if (pinr_offset != 0U) {
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uint32_t pinr_msk;
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pinr_msk = 0xFFU << (8U * FIELD_GET(SF32LB_PINR_FIELD_MSK, pin));
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val = sys_read32(config->cfg + pinr_offset);
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val &= ~pinr_msk;
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val |= FIELD_PREP(pinr_msk, FIELD_GET(SF32LB_PAD_MSK, pin));
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sys_write32(val, config->cfg + pinr_offset);
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}
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/* configure HPSYS_PINMUX */
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switch (FIELD_GET(SF32LB_PORT_MSK, pin)) {
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case SF32LB_PORT_SA:
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pad = config->pad_sa;
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break;
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case SF32LB_PORT_PA:
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pad = config->pad_pa;
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break;
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default:
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return -EINVAL;
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}
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pad += FIELD_GET(SF32LB_PAD_MSK, pin) * 4U;
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val = sys_read32(pad);
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val &= ~SF32LB_PINMUX_CFG_MSK;
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val |= (pin & (SF32LB_PINMUX_CFG_MSK & ~SF32LB_DS_MSK));
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val |= FIELD_PREP(SF32LB_DS_MSK, ds_reg);
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sys_write32(val, pad);
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return 0;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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ARG_UNUSED(reg);
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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int ret;
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ret = pinctrl_configure_pin(pins[i]);
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if (ret < 0) {
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return ret;
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}
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}
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return 0;
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}
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static int sf32lb52x_pinctrl_init(const struct device *dev)
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{
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const struct sf32lb52x_pinctrl_config *const config = dev->config;
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if (!sf32lb_clock_is_ready_dt(&config->clock)) {
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return -ENODEV;
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}
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return sf32lb_clock_control_on_dt(&config->clock);
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}
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static const struct sf32lb52x_pinctrl_config config = {
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.pad_sa = DT_INST_REG_ADDR_BY_NAME(0, pad_sa),
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.pad_pa = DT_INST_REG_ADDR_BY_NAME(0, pad_pa),
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.cfg = DT_REG_ADDR(DT_INST_PHANDLE(0, sifli_cfg)),
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.clock = SF32LB_CLOCK_DT_INST_SPEC_GET(0),
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};
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DEVICE_DT_INST_DEFINE(0, sf32lb52x_pinctrl_init, NULL, NULL, &config, PRE_KERNEL_1,
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, NULL);
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