Combine the load and noload cache regions for a single MPU aligned block. This is required to have an MPU region with a size that is a power of 2. Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Combine the load and noload cache regions for a single MPU aligned block. This is required to have an MPU region with a size that is a power of 2. Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>