1e33786dc4
Ports the snps_nsim SoC configuration to hardware model version 2 Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
54 lines
825 B
Plaintext
54 lines
825 B
Plaintext
# Copyright (c) 2018 Synopsys, Inc. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NSIM_EM7D_V22
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config CPU_EM4_FPUDA
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default y
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config NUM_IRQ_PRIO_LEVELS
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# This processor supports 4 priority levels:
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# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
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default 4
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config NUM_IRQS
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# must be > the highest interrupt number used
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default 30
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config ARC_MPU_VER
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default 2
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config RGF_NUM_BANKS
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default 1
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 5000000
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config HARVARD
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default y
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config ARC_FIRQ
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default y
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config CACHE_MANAGEMENT
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default y
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if (ARC_MPU_VER = 2)
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config MAIN_STACK_SIZE
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default 2048
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config IDLE_STACK_SIZE
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default 2048
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config ZTEST_STACK_SIZE
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default 2048
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depends on ZTEST
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endif # ARC_MPU_VER
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config ARC_HAS_ACCL_REGS
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default y
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endif # SOC_NSIM_EM
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