1e33786dc4
Ports the snps_nsim SoC configuration to hardware model version 2 Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
31 lines
558 B
Plaintext
31 lines
558 B
Plaintext
# Copyright (c) 2021 Synopsys, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NSIM_HS6X_SMP
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config CPU_HS6X
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default y
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config NUM_IRQ_PRIO_LEVELS
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# This processor supports 16 priority levels:
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default 2
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config NUM_IRQS
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# must be > the highest interrupt number used
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default 30
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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# SMP simulation is slower than single core, 1 Mhz seems reasonable match with wallclock
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default 1000000
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config CACHE_MANAGEMENT
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default y
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config ARC_CONNECT
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default y
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config MP_MAX_NUM_CPUS
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default 2
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endif # SOC_NSIM_HS6X_SMP
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