3f08e714b2
Align `ace` to 'intel_adsp_ace` SoC Series name and value to match the new HWMv2 compliance check, also renaming: SOC_SERIES_INTEL_ACE --> SOC_SERIES_INTEL_ADSP_ACE Signed-off-by: Dmitrii Golovanov <dmitrii.golovanov@intel.com>
66 lines
1.0 KiB
Plaintext
66 lines
1.0 KiB
Plaintext
# Copyright (c) 2022-2024 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_INTEL_ADSP_ACE
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config SMP
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default y
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config POWER_DOMAIN
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default y
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# MTL leaves the upper mapping in the same spot as cAVS, but moves the
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# lower one inexplicably.
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config XTENSA_UNCACHED_REGION
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default 2
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# Parameters for gen_isr_tables.py:
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config 2ND_LVL_INTR_00_OFFSET
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default 4
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config MULTI_LEVEL_INTERRUPTS
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default y
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config MAX_IRQ_PER_AGGREGATOR
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default 29
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config NUM_2ND_LEVEL_AGGREGATORS
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default 1
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config 2ND_LVL_ISR_TBL_OFFSET
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default 9
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config 2ND_LEVEL_INTERRUPTS
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default y
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config XTENSA_TIMER
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default n
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config XTENSA_TIMER_ID
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default 0
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 393216000 if XTENSA_TIMER
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default 38400000 if INTEL_ADSP_TIMER
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config SYS_CLOCK_TICKS_PER_SEC
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default 12000
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config XTENSA_CCOUNT_HZ
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default 393216000
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config DYNAMIC_INTERRUPTS
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default y
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if LOG
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config LOG_BACKEND_ADSP
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default y
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endif # LOG
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rsource "Kconfig.defconfig.ace*"
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endif # SOC_SERIES_INTEL_ADSP_ACE
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