84484e6707
Convert warp7 board to HWMv2. This board was originally ported using the iMX7D SOC (despite the fact that board uses an iMX7S SOC). For HWMv2, this board continues to use the IMX7D SOC port, since only the M4 core is enabled. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
88 lines
1.7 KiB
Plaintext
88 lines
1.7 KiB
Plaintext
/*
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* Copyright 2022 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/nxp_imx7d_m4.dtsi>
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#include <nxp/nxp_imx/mimx7d-pinctrl.dtsi>
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&pinctrl {
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uart2_default: uart2_default {
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group0 {
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pinmux = <&mx7d_pad_uart2_rx_data__uart2_dte_tx>,
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<&mx7d_pad_uart2_tx_data__uart2_dte_rx>;
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bias-pull-up;
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bias-pull-up-value = "100k";
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input-schmitt-enable;
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slew-rate = "slow";
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drive-strength = "x1";
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};
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};
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uart6_default: uart6_default {
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group0 {
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pinmux = <&mx7d_pad_ecspi1_sclk__uart6_dce_rx>,
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<&mx7d_pad_ecspi1_mosi__uart6_dce_tx>;
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bias-pull-up;
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bias-pull-up-value = "100k";
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input-schmitt-enable;
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slew-rate = "slow";
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drive-strength = "x1";
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};
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};
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i2c1_default: i2c1_default {
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group0 {
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pinmux = <&mx7d_pad_i2c1_scl__i2c1_scl>,
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<&mx7d_pad_i2c1_sda__i2c1_sda>;
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bias-pull-up;
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bias-pull-up-value = "100k";
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input-schmitt-enable;
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slew-rate = "slow";
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drive-strength = "x1";
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input-enable;
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};
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};
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i2c2_default: i2c2_default {
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group0 {
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pinmux = <&mx7d_pad_i2c2_scl__i2c2_scl>,
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<&mx7d_pad_i2c2_sda__i2c2_sda>;
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bias-pull-up;
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bias-pull-up-value = "100k";
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input-schmitt-enable;
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slew-rate = "slow";
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drive-strength = "x1";
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input-enable;
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};
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};
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i2c3_default: i2c3_default {
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group0 {
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pinmux = <&mx7d_pad_i2c3_scl__i2c3_scl>,
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<&mx7d_pad_i2c3_sda__i2c3_sda>;
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bias-pull-up;
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bias-pull-up-value = "100k";
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input-schmitt-enable;
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slew-rate = "slow";
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drive-strength = "x1";
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input-enable;
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};
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};
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i2c4_default: i2c4_default {
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group0 {
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pinmux = <&mx7d_pad_i2c4_scl__i2c4_scl>,
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<&mx7d_pad_i2c4_sda__i2c4_sda>;
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bias-pull-up;
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bias-pull-up-value = "100k";
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input-schmitt-enable;
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slew-rate = "slow";
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drive-strength = "x1";
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input-enable;
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};
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};
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};
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