4e0b47a85e
Imply XIP from the SoC config to make XIP the default to match the behaviour between Cortex-M33 and Hazard3 variants. This fixescbe6a716d3, which stopped selecting XIP at the SoC level. Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com> (cherry picked from commite3ef835ffe)
67 lines
1.5 KiB
Plaintext
67 lines
1.5 KiB
Plaintext
# Raspberry Pi RP235XX MCU line
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# Copyright (c) 2024 Andrew Featherstone
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RP2350
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select HAS_RPI_PICO
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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select SOC_RESET_HOOK
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imply XIP
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config SOC_RP2350A_HAZARD3
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select HAS_FLASH_LOAD_OFFSET
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select INCLUDE_RESET_VECTOR
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select RISCV
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZBA
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select RISCV_ISA_EXT_ZBS
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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config SOC_RP2350A_M33
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select ARM
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select ARM_TRUSTZONE_M
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_MPU
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select CPU_HAS_ARM_SAU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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config SOC_RP2350B_HAZARD3
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select HAS_FLASH_LOAD_OFFSET
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select INCLUDE_RESET_VECTOR
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select RISCV
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_A
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZBA
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select RISCV_ISA_EXT_ZBS
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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config SOC_RP2350B_M33
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select ARM
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select ARM_TRUSTZONE_M
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_VTOR
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_MPU
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select CPU_HAS_ARM_SAU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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config RP2_REQUIRES_IMAGE_DEFINITION_BLOCK
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bool
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default y
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depends on SOC_SERIES_RP2350
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help
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Include an Image Definition Block (IMAGE_DEF) to enable the bootroom in
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RP23XX devices to consider this a valid image in flash.
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