3ab62f13b8
The HAL used by the SiWx91x SoC implements a mechanism to protect
atomic sections. Since this HAL also supports a zero-latency
interrupt (ZLI) mechanism, we need to ensure the same number of
bits are used for ZLI interrupts.
The interrupt priority level (2) depends on a hardcoded value in the
Simplicity SDK (CORE_ATOMIC_BASE_PRIORITY_LEVEL).
Without this fix, arch_irq_lock (which sets the BASEPRI register to
0x4 when zero-latency interrupts are not enabled) is overridden by
CORE_EnterAtomic in the HAL, which sets BASEPRI to 0xC since the HAL
does not use the BASEPRI_MAX function. IRQ might then fires since it's
register with a lowest priority in Zephyr.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
(cherry picked from commit 87ab3e337a)
61 lines
1.2 KiB
Plaintext
61 lines
1.2 KiB
Plaintext
# Copyright (c) 2024 Silicon Laboratories Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_SILABS_SIWX91X
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configdefault CORTEX_M_SYSTICK
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default n if SILABS_SLEEPTIMER_TIMER
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configdefault SYS_CLOCK_TICKS_PER_SEC
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default 128 if !TICKLESS_KERNEL && SILABS_SLEEPTIMER_TIMER
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default 1024 if SILABS_SLEEPTIMER_TIMER
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configdefault UART_NS16550_DW8250_DW_APB
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default y
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configdefault ZERO_LATENCY_IRQS
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default y
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configdefault ZERO_LATENCY_LEVELS
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default 2
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if PM_DEVICE
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configdefault PM_DEVICE_RUNTIME
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default y
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configdefault POWER_DOMAIN
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default y
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endif # PM_DEVICE
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if SILABS_SIWX91X_NWP
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# WiseConnect create threads with realtime priority. Default (10kHz) clock tick
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# prevent proper use of the system with these threads.
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config SYS_CLOCK_TICKS_PER_SEC
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default 1024
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# Wiseconnect needs more than 1024 bytes of main stack size to initialize
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# (especially with PM)
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configdefault MAIN_STACK_SIZE
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default 2048
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config NUM_PREEMPT_PRIORITIES
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default 56
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config CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT
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default 2
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config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE
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default 1024
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config CMSIS_V2_THREAD_MAX_STACK_SIZE
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default 2048
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endif
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rsource "*/Kconfig.defconfig"
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endif # SOC_FAMILY_SILABS_SIWX91X
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