92eadf06b8
Ports the SoC configuration to hardware model version 2 Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
22 lines
577 B
Plaintext
22 lines
577 B
Plaintext
# Copyright (c) 2023 Rivos Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_OPENTITAN
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select ATOMIC_OPERATIONS_C
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select INCLUDE_RESET_VECTOR
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select RISCV_ISA_RV32I
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select RISCV_ISA_EXT_M
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select RISCV_ISA_EXT_C
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select RISCV_ISA_EXT_ZICSR
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select RISCV_ISA_EXT_ZIFENCEI
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select RISCV_ISA_EXT_ZBA
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select RISCV_ISA_EXT_ZBB
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select RISCV_ISA_EXT_ZBC
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select RISCV_ISA_EXT_ZBS
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select RISCV
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select RISCV_PRIVILEGED
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select RISCV_HAS_PLIC
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# OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode.
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select RISCV_VECTORED_MODE
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select GEN_IRQ_VECTOR_TABLE
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