92eadf06b8
Ports the SoC configuration to hardware model version 2 Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
25 lines
352 B
Plaintext
25 lines
352 B
Plaintext
# Copyright (c) 2023 Rivos Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_OPENTITAN
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 1000000
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config RISCV_SOC_INTERRUPT_INIT
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default y
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config RISCV_GP
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default y
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config 2ND_LVL_ISR_TBL_OFFSET
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default 32
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config 2ND_LVL_INTR_00_OFFSET
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default 11
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config NUM_IRQS
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default 256
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endif # SOC_OPENTITAN
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