b84bdbcee3
The new node is called "npu_cache". This way a possibility is offered to choose - thru an overlay - if to enable the NPU cache or not. This new node has a dependency with node "npu", so the NPU cache's status is taken into account only in case node "npu" has status "okay". Default status value of "npu_cache" is "okay" (i.e. enable the NPU cache). Signed-off-by: Wolfgang Betz <wolfgang.betz@st.com>
64 lines
2.1 KiB
C
64 lines
2.1 KiB
C
/*
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* Copyright (c) 2026 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_npu_cache
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <soc.h>
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#define NPU_CACHE_NODE DT_DRV_INST(0)
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#define NPU_CACHE_BASE DT_REG_ADDR(NPU_CACHE_NODE)
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#define NPU_CACHE_CTRL_REG_OFFSET 0x0
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#define NPU_CACHE_ERR_IRQ_OFFSET 0x8
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#define NPU_CACHE_DISABLE 0x0
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#define NPU_CACHE_ENABLE 0x1
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#define NPU_CACHE_CNT_ENABLE 0x33330000
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#define NPU_CACHE_CNT_RESET 0xCCCC0000
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#define NPU_CACHE_ERR_IRQ_ENABLE BIT(2)
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/*
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* Define npu_cache_stm32_enable and instantiate the device only if both
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* the NPU and NPU cache nodes are enabled in the device tree.
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* This avoids unused function warnings when the cache is disabled.
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*/
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#if DT_NODE_HAS_STATUS_OKAY(DT_INST(0, st_stm32_npu)) && \
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DT_NODE_HAS_STATUS_OKAY(DT_INST(0, st_stm32_npu_cache))
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static int npu_cache_stm32_enable(const struct device *dev)
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{
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/* Disable cache */
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sys_write32(NPU_CACHE_DISABLE, NPU_CACHE_BASE + NPU_CACHE_CTRL_REG_OFFSET);
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k_busy_wait(5 * USEC_PER_MSEC); /* 5ms delay */
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/* Enable cache */
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sys_write32(NPU_CACHE_ENABLE, NPU_CACHE_BASE + NPU_CACHE_CTRL_REG_OFFSET);
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/* Enable cache counters */
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sys_set_bits(NPU_CACHE_BASE + NPU_CACHE_CTRL_REG_OFFSET, NPU_CACHE_CNT_ENABLE);
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/* Reset cache counters */
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sys_set_bits(NPU_CACHE_BASE + NPU_CACHE_CTRL_REG_OFFSET, NPU_CACHE_CNT_RESET);
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/* Enable cache error interrupt */
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sys_write32(NPU_CACHE_ERR_IRQ_ENABLE, NPU_CACHE_BASE + NPU_CACHE_ERR_IRQ_OFFSET);
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return 0;
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}
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DEVICE_DT_INST_DEFINE(0, npu_cache_stm32_enable, NULL, NULL, NULL, POST_KERNEL,
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CONFIG_STM32N6_NPU_CACHE_INIT_PRIORITY, NULL);
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/*
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* Guarantee that initialization priority for the NPU is higher than the one of the NPU cache (aka
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* CACHEAXI)
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*/
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BUILD_ASSERT(CONFIG_STM32N6_NPU_CACHE_INIT_PRIORITY > CONFIG_STM32N6_NPU_INIT_PRIORITY,
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"NPU cache initialization must run after NPU driver initialization");
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#endif /* st_stm32_npu && st_stm32_npu_cache */
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