3cbabecfcc
Pinmux driver almost certainly should be initialized before the rest of hardware devices (which may need specific pins already configured for them), and usually after generic GPIO drivers. Thus, its priority should be between KERNEL_INIT_PRIORITY_DEFAULT (default 40) and KERNEL_INIT_PRIORITY_DEVICE (default 50). Thus, we set PINMUX_INIT_PRIORITY to 45. There are exceptions to the rule above for particular boards. For example, BOARD=galileo has GPIO and pinmuxer on I2C bus and thus overrides PINMUX_INIT_PRIORITY to be much higher. Note that while PINMUX_INIT_PRIORITY was defined previously (at 60), it was used only for galileo, which overrides it anyway. This fix was prompted by investigation why eth_ksdk driver was non-functional after kernel priorities re-hashing: both eth_ksdk and pinmux used the same priority, and eth_ksdk happened to run before pinmux. While bumping eth_ksdk priority would help in the particular case, the same would likely reoccur with other drivers like I2C, SPI, etc. Change-Id: Ie5ca3135c1ee2fe8d9cf48d5c12e62eac63487f7 Signed-off-by: Paul Sokolovsky <paul.sokolovsky@linaro.org>
70 lines
1.9 KiB
C
70 lines
1.9 KiB
C
/* pinmux_board_hexiwear.c - pin out mapping for the NXP Hexiwear board */
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/*
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* Copyright (c) 2016 Intel Corporation
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <nanokernel.h>
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#include <device.h>
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#include <init.h>
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#include <sys_io.h>
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#include <pinmux.h>
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#include <pinmux/pinmux.h>
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#include <pinmux/k64/pinmux.h>
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/*
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* I/O pin configuration
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*/
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/*
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* Alter this table to change the default pin settings on the NXP Hexiwear
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* boards. Specifically, change the PINMUX_* values to represent the
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* functionality desired.
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*/
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static const struct pin_config mux_config[] = {
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/* pin, selected mode */
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/* RGB */
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{ K64_PIN_PTC8, K64_PINMUX_FUNC_GPIO},
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{ K64_PIN_PTC9, K64_PINMUX_FUNC_GPIO},
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{ K64_PIN_PTD0, K64_PINMUX_FUNC_GPIO},
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/* I2C1 - accel/mag, gyro, pressure */
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{ K64_PIN_PTC10, (K64_PINMUX_ALT_2 | K64_PINMUX_OPEN_DRN_ENABLE)},
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{ K64_PIN_PTC11, (K64_PINMUX_ALT_2 | K64_PINMUX_OPEN_DRN_ENABLE)},
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/* FXOS8700 INT1 */
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{ K64_PIN_PTC1, K64_PINMUX_FUNC_GPIO},
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/* UART4 - BLE */
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{ K64_PIN_PTE25, K64_PINMUX_ALT_3 },
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{ K64_PIN_PTE24, K64_PINMUX_ALT_3 },
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};
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static int hexiwear_pin_init(struct device *arg)
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{
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ARG_UNUSED(arg);
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/* configure the pins from the default mapping above */
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for (int i = 0; i < ARRAY_SIZE(mux_config); i++) {
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_fsl_k64_set_pin(mux_config[i].pin_num, mux_config[i].mode);
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}
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return 0;
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}
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SYS_INIT(hexiwear_pin_init, POST_KERNEL, CONFIG_PINMUX_INIT_PRIORITY);
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