ee8f9915a4
This selects CONFIG_CPU_HAS_MPU for nsim_vpx5 series SoC as it supports ARC MPUv3. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
37 lines
625 B
Plaintext
37 lines
625 B
Plaintext
# Copyright (c) 2023 Synopsys, Inc. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NSIM_VPX5
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config CPU_HS3X
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default y
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config NUM_IRQ_PRIO_LEVELS
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# This processor supports 16 priority levels:
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# 0 for Fast Interrupts (FIRQs) and 1-15 for Regular Interrupts (IRQs).
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default 4
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config NUM_IRQS
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# must be > the highest interrupt number used
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default 24
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config RGF_NUM_BANKS
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default 1
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 5000000
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config HARVARD
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default y
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config ARC_FIRQ
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default n
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config CACHE_MANAGEMENT
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default y
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config ARC_MPU_VER
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default 3 if ARC_MPU_ENABLE
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endif # SOC_NSIM_VPX5
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