fd49b1749e
Convert iMX6 SoloX core to HWMv2. This port currently only supports the M4 core (as it did in HWMv1) Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
80 lines
2.6 KiB
C
80 lines
2.6 KiB
C
/*
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* Copyright (c) 2021, Antonio Tessarolo
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <ccm_imx6sx.h>
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#include <ccm_analog_imx6sx.h>
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#include "soc_clk_freq.h"
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#ifdef CONFIG_PWM_IMX
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uint32_t get_pwm_clock_freq(PWM_Type *base)
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{
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uint32_t root;
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uint32_t hz;
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uint32_t divPerclkPodf, divIpgPodf, divAhbPodf, divPeriphClk2Podf;
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/* Different instance has the same clock root, it's different from i.mx7d. */
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/* Get the clock root according to the mux node of clock tree. */
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if (CCM_GetRootMux(CCM, ccmRootPerclkClkSel) ==
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ccmRootmuxPerclkClkOsc24m) {
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root = ccmRootmuxPerclkClkOsc24m;
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hz = 24000000;
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divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
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divIpgPodf = 0;
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divAhbPodf = 0;
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divPeriphClk2Podf = 0;
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} else if (CCM_GetRootMux(CCM, ccmRootPeriphClkSel) ==
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ccmRootmuxPeriphClkPrePeriphClkSel) {
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root = CCM_GetRootMux(CCM, ccmRootPrePeriphClkSel);
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/* Here do not show all the clock root source,
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* if user use other clock root source, such as PLL2_PFD2, please
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* add it as follows according to the clock tree of CCM in reference manual.
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*/
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switch (root) {
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case ccmRootmuxPrePeriphClkPll2:
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hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllSysControl);
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divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
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divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
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divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
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divPeriphClk2Podf = 0;
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break;
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default:
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return 0;
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}
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} else if (CCM_GetRootMux(CCM, ccmRootPeriphClk2Sel) ==
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ccmRootmuxPeriphClk2OSC24m) {
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root = ccmRootmuxPeriphClk2OSC24m;
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hz = 24000000;
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divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
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divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
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divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
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divPeriphClk2Podf = CCM_GetRootDivider(CCM, ccmRootPeriphClk2Podf);
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} else {
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root = CCM_GetRootMux(CCM, ccmRootPll3SwClkSel);
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/* Here do not show all the clock root source,
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* if user use other clock root source, such as PLL3_BYP, please
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* add it as follows according to the clock tree of CCM in reference manual.
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*/
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switch (root) {
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case ccmRootmuxPll3SwClkPll3:
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hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllUsb1Control);
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divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf);
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divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf);
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divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf);
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divPeriphClk2Podf =
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CCM_GetRootDivider(CCM, ccmRootPeriphClk2Podf);
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break;
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default:
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return 0;
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}
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}
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return hz / (divPerclkPodf + 1) / (divIpgPodf + 1) /
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(divAhbPodf + 1) / (divPeriphClk2Podf + 1);
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}
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#endif /* CONFIG_PWM_IMX */
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