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media: ccs-pll: Document the CCS PLL flags

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Document the CCS PLL flags with short comments. The CCS spec has more
information on them while the added documentation helps finding the
relevant information in the CCS spec.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
This commit is contained in:
Sakari Ailus
2025-04-16 14:08:56 +03:00
committed by Hans Verkuil
parent de6514694b
commit 220ea1432a
2 changed files with 25 additions and 4 deletions
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2
drivers/media/i2c/ccs-pll.c
View File

@@ -129,8 +129,8 @@ static void print_pll_flags(struct device *dev, struct ccs_pll *pll)
{
dev_dbg(dev, "PLL flags%s%s%s%s%s%s%s%s%s%s%s\n",
pll->flags & PLL_FL(OP_PIX_CLOCK_PER_LANE) ? " op-pix-clock-per-lane" : "",
pll->flags & PLL_FL(NO_OP_CLOCKS) ? " no-op-clocks" : "",
pll->flags & PLL_FL(EVEN_PLL_MULTIPLIER) ? " even-pll-multiplier" : "",
pll->flags & PLL_FL(NO_OP_CLOCKS) ? " no-op-clocks" : "",
pll->flags & PLL_FL(LANE_SPEED_MODEL) ? " lane-speed" : "",
pll->flags & PLL_FL(EXT_IP_PLL_DIVIDER) ?
" ext-ip-pll-divider" : "",

27
drivers/media/i2c/ccs-pll.h
View File

@@ -18,19 +18,40 @@
#define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00
#define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01
/* Old SMIA and implementation specific flags */
/* op pix clock is for all lanes in total normally */
/* Old SMIA and implementation specific flags. */
/* OP PIX clock is for all lanes in total normally. */
#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0)
#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1)
/* If set, the PLL multipliers are required to be even. */
#define CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER BIT(3)
/* CCS PLL flags */
/* The sensor doesn't have OP clocks at all. */
#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1)
/* System speed model if this flag is unset. */
#define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2)
/* If set, the pre-PLL divider may have odd values, too. */
#define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4)
/*
* If set, the OP PIX clock doesn't have to exactly match with data rate, it may
* be higher. See "OP Domain Formulas" in MIPI CCS 1.1 spec.
*/
#define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV BIT(5)
/* If set, the VT domain may run faster than the OP domain. */
#define CCS_PLL_FLAG_FIFO_DERATING BIT(6)
/* If set, the VT domain may run slower than the OP domain. */
#define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7)
/* If set, the PLL tree has two PLLs instead of one. */
#define CCS_PLL_FLAG_DUAL_PLL BIT(8)
/*
* If set, the OP SYS clock is a dual data rate clock, transferring two bits per
* cycle instead of one.
*/
#define CCS_PLL_FLAG_OP_SYS_DDR BIT(9)
/*
* If set, the OP PIX clock is a dual data rate clock, transferring two pixels
* per cycle instead of one.
*/
#define CCS_PLL_FLAG_OP_PIX_DDR BIT(10)
/**