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dt-bindings: clock: qcom: Add SM8750 video clock controller

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Add compatible string for SM8750 video clock controller and the bindings
for SM8750 Qualcomm SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20251118-sm8750-videocc-v2-v4-4-049882a70c9f@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Taniya Das
2025-11-18 12:47:08 +05:30
committed by Bjorn Andersson
parent aa788d3b47
commit b190eaea57
2 changed files with 44 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller on SM8450
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
- Taniya Das <taniya.das@oss.qualcomm.com>
- Jagadeesh Kona <quic_jkona@quicinc.com>
description: |
@@ -17,6 +17,7 @@ description: |
See also:
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
include/dt-bindings/clock/qcom,sm8750-videocc.h
properties:
compatible:
@@ -25,6 +26,7 @@ properties:
- qcom,sm8475-videocc
- qcom,sm8550-videocc
- qcom,sm8650-videocc
- qcom,sm8750-videocc
- qcom,x1e80100-videocc
clocks:
@@ -61,6 +63,7 @@ allOf:
enum:
- qcom,sm8450-videocc
- qcom,sm8550-videocc
- qcom,sm8750-videocc
then:
required:
- required-opps

40
include/dt-bindings/clock/qcom,sm8750-videocc.h Normal file
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@@ -0,0 +1,40 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8750_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8750_H
/* VIDEO_CC clocks */
#define VIDEO_CC_AHB_CLK 0
#define VIDEO_CC_AHB_CLK_SRC 1
#define VIDEO_CC_MVS0_CLK 2
#define VIDEO_CC_MVS0_CLK_SRC 3
#define VIDEO_CC_MVS0_DIV_CLK_SRC 4
#define VIDEO_CC_MVS0_FREERUN_CLK 5
#define VIDEO_CC_MVS0_SHIFT_CLK 6
#define VIDEO_CC_MVS0C_CLK 7
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8
#define VIDEO_CC_MVS0C_FREERUN_CLK 9
#define VIDEO_CC_MVS0C_SHIFT_CLK 10
#define VIDEO_CC_PLL0 11
#define VIDEO_CC_SLEEP_CLK 12
#define VIDEO_CC_SLEEP_CLK_SRC 13
#define VIDEO_CC_XO_CLK 14
#define VIDEO_CC_XO_CLK_SRC 15
/* VIDEO_CC power domains */
#define VIDEO_CC_MVS0_GDSC 0
#define VIDEO_CC_MVS0C_GDSC 1
/* VIDEO_CC resets */
#define VIDEO_CC_INTERFACE_BCR 0
#define VIDEO_CC_MVS0_BCR 1
#define VIDEO_CC_MVS0C_CLK_ARES 2
#define VIDEO_CC_MVS0C_BCR 3
#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 4
#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 5
#define VIDEO_CC_XO_CLK_ARES 6
#endif