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riscv: dts: starfive: jh7110: add DMC memory controller

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Add JH7110 SoC DDR external memory controller.

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

[ upstream commit: 7114969021ec5c4c0f3df1da3a8790f75dda92e2 ]

(cherry picked from commit 8d5c520b73b7c29b714f75e99ed48baa55fc5fa1)
This commit is contained in:
E Shattow
2025-10-15 03:22:45 -07:00
committed by Leo Yu-Chi Liang
parent 417ad9b0c7
commit 2b26cda14f
1 changed files with 12 additions and 0 deletions
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12
dts/upstream/src/riscv/starfive/jh7110.dtsi
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@@ -931,6 +931,18 @@
<&syscrg JH7110_SYSRST_WDT_CORE>;
};
memory-controller@15700000 {
compatible = "starfive,jh7110-dmc";
reg = <0x0 0x15700000 0x0 0x10000>,
<0x0 0x13000000 0x0 0x10000>;
clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>;
clock-names = "pll";
resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
<&syscrg JH7110_SYSRST_DDR_OSC>,
<&syscrg JH7110_SYSRST_DDR_APB>;
reset-names = "axi", "osc", "apb";
};
crypto: crypto@16000000 {
compatible = "starfive,jh7110-crypto";
reg = <0x0 0x16000000 0x0 0x4000>;