Merge patch series "rockchip: ringneck-px30: anticipate breakage with v6.16-rc1 DT"

Quentin Schulz <foss+uboot@0leil.net> says:

v6.16-rc1 will bring an incompatible change to the Device Tree of PX30
Ringneck which will break Ethernet support.

Unfortunately, the designware net driver's logic doesn't seem to allow
having the old Device Tree (without MDIO bus and Ethernet PHY nodes)
with DM_MDIO and DM_ETH_PHY enabled so there cannot be a smooth
transition.

Since this is going to bite me in a few months time, let's just break
and fix it now in a couple of commits so I don't have to think about it
later :)

This can be cleanly applied on master or next, I have absolutely zero
preference on the branch this should be merged in (my opinion is that
it's too late in the 2024.07 cycle to bring this in :) ).

Link: https://lore.kernel.org/r/20250611-ringneck-mdio-v1-0-529a40a0f966@cherry.de

configs/ringneck-px30_defconfig

@@ -83,6 +83,8 @@ CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_PHY_TI_GENERIC=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_ETH_PHY=y
 CONFIG_PHY_GIGE=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y

dts/upstream/src/arm64/rockchip/px30-ringneck.dtsi

@@ -83,9 +83,7 @@
 
 /* On-module TI DP83825I PHY but no connector, enable in carrierboard */
 &gmac {
-	snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
-	snps,reset-active-low;
-	snps,reset-delays-us = <0 50000 50000>;
+	phy-handle = <&dp83825>;
 	phy-supply = <&vcc_3v3>;
 	clock_in_out = "output";
 };
@@ -344,6 +342,18 @@
 	status = "okay";
 };
 
+&mdio {
+	dp83825: ethernet-phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&phy_rst>;
+		reset-assert-us = <50000>;
+		reset-deassert-us = <50000>;
+		reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+	};
+};
+
 &pinctrl {
 	emmc {
 		emmc_reset: emmc-reset {
@@ -351,6 +361,12 @@
 		};
 	};
 
+	ethernet {
+		phy_rst: phy-rst {
+			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	leds {
 		module_led_pin: module-led-pin {
 			rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;

dts/upstream/src/arm64/rockchip/px30.dtsi

@@ -985,6 +985,12 @@
 		resets = <&cru SRST_GMAC_A>;
 		reset-names = "stmmaceth";
 		status = "disabled";
+
+		mdio: mdio {
+			compatible = "snps,dwmac-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
 	};
 
 	sdmmc: mmc@ff370000 {