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clk: mediatek: add array size fields to clk trees

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Add num_plls, num_fclks, num_fdivs, num_muxes, and num_gates fields to
the mtk_clk_tree struct and populate them in the clk trees for all
existing drivers.

Currently, there is no bounds checking when accessing the arrays in
the clk tree structs. Adding these fields will allow for bounds checking
in the future.

Signed-off-by: David Lechner <dlechner@baylibre.com>
This commit is contained in:
David Lechner
2026-01-07 09:50:11 -06:00
committed by Tom Rini
parent 53c0d5b387
commit 3d54f47ae5
14 changed files with 77 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/clk/mediatek/clk-mt7622.c
View File

@@ -604,6 +604,8 @@ static const struct mtk_clk_tree mt7622_apmixed_clk_tree = {
.plls = apmixed_plls,
.gates_offs = CLK_APMIXED_MAIN_CORE_EN,
.gates = apmixed_cgs,
.num_plls = ARRAY_SIZE(apmixed_plls),
.num_gates = ARRAY_SIZE(apmixed_cgs),
};
static const struct mtk_clk_tree mt7622_infra_clk_tree = {
@@ -612,6 +614,8 @@ static const struct mtk_clk_tree mt7622_infra_clk_tree = {
.gates_offs = CLK_INFRA_DBGCLK_PD,
.muxes = infra_muxes,
.gates = infra_cgs,
.num_muxes = ARRAY_SIZE(infra_muxes),
.num_gates = ARRAY_SIZE(infra_cgs),
};
static const struct mtk_clk_tree mt7622_peri_clk_tree = {
@@ -620,6 +624,8 @@ static const struct mtk_clk_tree mt7622_peri_clk_tree = {
.gates_offs = CLK_PERI_THERM_PD,
.muxes = peri_muxes,
.gates = peri_cgs,
.num_muxes = ARRAY_SIZE(peri_muxes),
.num_gates = ARRAY_SIZE(peri_cgs),
};
static const struct mtk_clk_tree mt7622_clk_tree = {
@@ -629,6 +635,9 @@ static const struct mtk_clk_tree mt7622_clk_tree = {
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
.num_fclks = ARRAY_SIZE(top_fixed_clks),
.num_fdivs = ARRAY_SIZE(top_fixed_divs),
.num_muxes = ARRAY_SIZE(top_muxes),
};
static int mt7622_mcucfg_probe(struct udevice *dev)

6
drivers/clk/mediatek/clk-mt7623.c
View File

@@ -997,6 +997,7 @@ static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = {
.xtal2_rate = 26 * MHZ,
.id_offs_map = pll_id_offs_map,
.plls = apmixed_plls,
.num_plls = ARRAY_SIZE(apmixed_plls),
};
static const struct mtk_clk_tree mt7623_topckgen_clk_tree = {
@@ -1007,6 +1008,9 @@ static const struct mtk_clk_tree mt7623_topckgen_clk_tree = {
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
.num_fclks = ARRAY_SIZE(top_fixed_clks),
.num_fdivs = ARRAY_SIZE(top_fixed_divs),
.num_muxes = ARRAY_SIZE(top_muxes),
};
static int mt7623_mcucfg_probe(struct udevice *dev)
@@ -1063,6 +1067,8 @@ static const struct mtk_clk_tree mt7623_clk_peri_tree = {
.gates_offs = peri_id_offs_map[CLK_PERI_NFI],
.muxes = peri_muxes,
.gates = peri_cgs,
.num_muxes = ARRAY_SIZE(peri_muxes),
.num_gates = ARRAY_SIZE(peri_cgs),
.xtal_rate = 26 * MHZ,
};

8
drivers/clk/mediatek/clk-mt7629.c
View File

@@ -572,6 +572,10 @@ static const struct mtk_clk_tree mt7629_clk_tree = {
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
.num_plls = ARRAY_SIZE(apmixed_plls),
.num_fclks = ARRAY_SIZE(top_fixed_clks),
.num_fdivs = ARRAY_SIZE(top_fixed_divs),
.num_muxes = ARRAY_SIZE(top_muxes),
};
static const struct mtk_clk_tree mt7629_peri_clk_tree = {
@@ -584,6 +588,10 @@ static const struct mtk_clk_tree mt7629_peri_clk_tree = {
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
.num_plls = ARRAY_SIZE(apmixed_plls),
.num_fclks = ARRAY_SIZE(top_fixed_clks),
.num_fdivs = ARRAY_SIZE(top_fixed_divs),
.num_muxes = ARRAY_SIZE(top_muxes),
};
static int mt7629_mcucfg_probe(struct udevice *dev)

7
drivers/clk/mediatek/clk-mt7981.c
View File

@@ -513,6 +513,7 @@ static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = {
.fdivs_offs = CLK_APMIXED_NR_CLK,
.xtal_rate = 40 * MHZ,
.fclks = fixed_pll_clks,
.num_fclks = ARRAY_SIZE(fixed_pll_clks),
};
static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {
@@ -521,6 +522,9 @@ static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
.num_fclks = ARRAY_SIZE(top_fixed_clks),
.num_fdivs = ARRAY_SIZE(top_fixed_divs),
.num_muxes = ARRAY_SIZE(top_muxes),
.flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN,
};
@@ -531,6 +535,9 @@ static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
.fdivs = infra_fixed_divs,
.muxes = infra_muxes,
.gates = infracfg_gates,
.num_fdivs = ARRAY_SIZE(infra_fixed_divs),
.num_muxes = ARRAY_SIZE(infra_muxes),
.num_gates = ARRAY_SIZE(infracfg_gates),
.flags = CLK_PARENT_INFRASYS,
};

7
drivers/clk/mediatek/clk-mt7986.c
View File

@@ -519,6 +519,7 @@ static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
.fdivs_offs = CLK_APMIXED_NR_CLK,
.xtal_rate = 40 * MHZ,
.fclks = fixed_pll_clks,
.num_fclks = ARRAY_SIZE(fixed_pll_clks),
.flags = CLK_PARENT_APMIXED,
};
@@ -528,6 +529,9 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
.num_fclks = ARRAY_SIZE(top_fixed_clks),
.num_fdivs = ARRAY_SIZE(top_fixed_divs),
.num_muxes = ARRAY_SIZE(top_muxes),
.flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN,
};
@@ -538,6 +542,9 @@ static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
.fdivs = infra_fixed_divs,
.muxes = infra_muxes,
.gates = infracfg_gates,
.num_fdivs = ARRAY_SIZE(infra_fixed_divs),
.num_muxes = ARRAY_SIZE(infra_muxes),
.num_gates = ARRAY_SIZE(infracfg_gates),
.flags = CLK_PARENT_INFRASYS,
};

5
drivers/clk/mediatek/clk-mt7987.c
View File

@@ -46,6 +46,7 @@ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = {
.fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
.fclks = apmixedsys_mtk_plls,
.num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls),
.flags = CLK_PARENT_APMIXED,
.xtal_rate = 40 * MHZ,
};
@@ -442,6 +443,8 @@ static const struct mtk_clk_tree mt7987_topckgen_clk_tree = {
.muxes_offs = CLK_TOP_NETSYS_SEL,
.fdivs = topckgen_mtk_fixed_factors,
.muxes = topckgen_mtk_muxes,
.num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors),
.num_muxes = ARRAY_SIZE(topckgen_mtk_muxes),
.flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN,
.xtal_rate = MT7987_XTAL_RATE,
};
@@ -765,6 +768,8 @@ static const struct mtk_clk_tree mt7987_infracfg_clk_tree = {
.gates_offs = CLK_INFRA_66M_GPT_BCK,
.muxes = infracfg_mtk_mux,
.gates = infracfg_mtk_gates,
.num_muxes = ARRAY_SIZE(infracfg_mtk_mux),
.num_gates = ARRAY_SIZE(infracfg_mtk_gates),
.flags = CLK_BYPASS_XTAL,
.xtal_rate = MT7987_XTAL_RATE,
};

6
drivers/clk/mediatek/clk-mt7988.c
View File

@@ -773,6 +773,7 @@ static const struct mtk_gate infracfg_mtk_gates[] = {
static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
.fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
.fclks = apmixedsys_mtk_plls,
.num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls),
.flags = CLK_PARENT_APMIXED,
.xtal_rate = 40 * MHZ,
};
@@ -783,6 +784,9 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
.fclks = topckgen_mtk_fixed_clks,
.fdivs = topckgen_mtk_fixed_factors,
.muxes = topckgen_mtk_muxes,
.num_fclks = ARRAY_SIZE(topckgen_mtk_fixed_clks),
.num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors),
.num_muxes = ARRAY_SIZE(topckgen_mtk_muxes),
.flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN,
.xtal_rate = 40 * MHZ,
};
@@ -792,6 +796,8 @@ static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
.gates_offs = CLK_INFRA_PCIE_PERI_26M_CK_P0,
.muxes = infracfg_mtk_mux,
.gates = infracfg_mtk_gates,
.num_muxes = ARRAY_SIZE(infracfg_mtk_mux),
.num_gates = ARRAY_SIZE(infracfg_mtk_gates),
.flags = CLK_BYPASS_XTAL,
.xtal_rate = 40 * MHZ,
};

4
drivers/clk/mediatek/clk-mt8183.c
View File

@@ -599,6 +599,10 @@ static const struct mtk_clk_tree mt8183_clk_tree = {
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
.num_plls = ARRAY_SIZE(apmixed_plls),
.num_fclks = ARRAY_SIZE(top_fixed_clks),
.num_fdivs = ARRAY_SIZE(top_fixed_divs),
.num_muxes = ARRAY_SIZE(top_muxes),
};
static const struct mtk_gate_regs infra0_cg_regs = {

4
drivers/clk/mediatek/clk-mt8188.c
View File

@@ -85,6 +85,7 @@ static const struct mtk_clk_tree mt8188_apmixedsys_clk_tree = {
.xtal_rate = 26 * MHZ,
.xtal2_rate = 26 * MHZ,
.plls = apmixed_plls,
.num_plls = ARRAY_SIZE(apmixed_plls),
};
static const struct mtk_fixed_clk top_fixed_clks[] = {
@@ -1364,6 +1365,9 @@ static const struct mtk_clk_tree mt8188_topckgen_clk_tree = {
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
.num_fclks = ARRAY_SIZE(top_fixed_clks),
.num_fdivs = ARRAY_SIZE(top_fixed_divs),
.num_muxes = ARRAY_SIZE(top_muxes),
};
static const struct mtk_gate_regs infra_ao0_cg_regs = {

4
drivers/clk/mediatek/clk-mt8365.c
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@@ -490,6 +490,10 @@ static const struct mtk_clk_tree mt8365_clk_tree = {
.fclks = top_fixed_clks,
.fdivs = top_divs,
.muxes = top_muxes,
.num_plls = ARRAY_SIZE(apmixed_plls),
.num_fclks = ARRAY_SIZE(top_fixed_clks),
.num_fdivs = ARRAY_SIZE(top_divs),
.num_muxes = ARRAY_SIZE(top_muxes),
};
/* topckgen cg */

4
drivers/clk/mediatek/clk-mt8512.c
View File

@@ -790,6 +790,10 @@ static const struct mtk_clk_tree mt8512_clk_tree = {
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
.num_plls = ARRAY_SIZE(apmixed_plls),
.num_fclks = ARRAY_SIZE(top_fixed_clks),
.num_fdivs = ARRAY_SIZE(top_fixed_divs),
.num_muxes = ARRAY_SIZE(top_muxes),
};
static int mt8512_apmixedsys_probe(struct udevice *dev)

4
drivers/clk/mediatek/clk-mt8516.c
View File

@@ -739,6 +739,10 @@ static const struct mtk_clk_tree mt8516_clk_tree = {
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
.num_plls = ARRAY_SIZE(apmixed_plls),
.num_fclks = ARRAY_SIZE(top_fixed_clks),
.num_fdivs = ARRAY_SIZE(top_fixed_divs),
.num_muxes = ARRAY_SIZE(top_muxes),
};
static int mt8516_apmixedsys_probe(struct udevice *dev)

4
drivers/clk/mediatek/clk-mt8518.c
View File

@@ -1495,6 +1495,10 @@ static const struct mtk_clk_tree mt8518_clk_tree = {
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
.num_plls = ARRAY_SIZE(apmixed_plls),
.num_fclks = ARRAY_SIZE(top_fixed_clks),
.num_fdivs = ARRAY_SIZE(top_fixed_divs),
.num_muxes = ARRAY_SIZE(top_muxes),
};
static int mt8518_apmixedsys_probe(struct udevice *dev)

5
drivers/clk/mediatek/clk-mtk.h
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@@ -260,6 +260,11 @@ struct mtk_clk_tree {
const struct mtk_fixed_factor *fdivs;
const struct mtk_composite *muxes;
const struct mtk_gate *gates;
const int num_plls;
const int num_fclks;
const int num_fdivs;
const int num_muxes;
const int num_gates;
u32 flags;
};