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drivers: firmware: update xilinx_pm_request to support max payload

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Currently xilinx_pm_request API supports four u32 payloads. However the
legacy SMC format supports five u32 request payloads and extended SMC
format supports six u32 request payloads. Add support for the same in
xilinx_pm_request API. Also add two dummy arguments to all the callers
of xilinx_pm_request.

The TF-A always fills seven u32 return payload so add support
for the same in xilinx_pm_request API.

Signed-off-by: Naman Trivedi <naman.trivedimanojbhai@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Acked-by: Senthil Nathan Thangaraj <senthilnathan.thangaraj@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5ae6b560741f3ca8b89059c4ebb87acf75b4718e.1756388537.git.michal.simek@amd.com
This commit is contained in:
Naman Trivedi
2025-08-28 15:42:22 +02:00
committed by Michal Simek
parent e7fe2c7bc6
commit 4146a31dce
20 changed files with 90 additions and 70 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/mach-zynqmp/aes.c
View File

@@ -47,7 +47,8 @@ int zynqmp_aes_operation(struct zynqmp_aes *aes)
roundup(sizeof(struct zynqmp_aes), ARCH_DMA_MINALIGN));
ret = xilinx_pm_request(PM_SECURE_AES, upper_32_bits((ulong)aes),
lower_32_bits((ulong)aes), 0, 0, ret_payload);
lower_32_bits((ulong)aes), 0, 0, 0, 0,
ret_payload);
if (ret || ret_payload[1]) {
printf("Failed: AES op status:0x%x, errcode:0x%x\n",
ret, ret_payload[1]);

4
arch/arm/mach-zynqmp/cpu.c
View File

@@ -205,7 +205,7 @@ int zynqmp_mmio_write(const u32 address,
#if defined(CONFIG_ZYNQMP_FIRMWARE)
else
return xilinx_pm_request(PM_MMIO_WRITE, address, mask,
value, 0, NULL);
value, 0, 0, 0, NULL);
#endif
return -EINVAL;
@@ -226,7 +226,7 @@ int zynqmp_mmio_read(const u32 address, u32 *value)
u32 ret_payload[PAYLOAD_ARG_CNT];
ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0,
0, ret_payload);
0, 0, 0, ret_payload);
*value = ret_payload[1];
}
#endif

10
arch/arm/mach-zynqmp/zynqmp.c
View File

@@ -57,7 +57,7 @@ static int do_zynqmp_verify_secure(struct cmd_tbl *cmdtp, int flag, int argc,
}
ret = xilinx_pm_request(PM_SECURE_IMAGE, src_lo, src_hi,
key_lo, key_hi, ret_payload);
key_lo, key_hi, 0, 0, ret_payload);
if (ret) {
printf("Failed: secure op status:0x%x\n", ret);
} else {
@@ -260,7 +260,7 @@ static int do_zynqmp_rsa(struct cmd_tbl *cmdtp, int flag, int argc,
ret = xilinx_pm_request(PM_SECURE_RSA, upper_32_bits((ulong)srcaddr),
lower_32_bits((ulong)srcaddr), srclen, rsaop,
ret_payload);
0, 0, ret_payload);
if (ret || ret_payload[1]) {
printf("Failed: RSA status:0x%x, errcode:0x%x\n",
ret, ret_payload[1]);
@@ -309,7 +309,7 @@ static int do_zynqmp_sha3(struct cmd_tbl *cmdtp, int flag,
srcaddr + roundup(srclen, ARCH_DMA_MINALIGN));
ret = xilinx_pm_request(PM_SECURE_SHA, 0, 0, 0,
ZYNQMP_SHA3_INIT, ret_payload);
ZYNQMP_SHA3_INIT, 0, 0, ret_payload);
if (ret || ret_payload[1]) {
printf("Failed: SHA INIT status:0x%x, errcode:0x%x\n",
ret, ret_payload[1]);
@@ -318,7 +318,7 @@ static int do_zynqmp_sha3(struct cmd_tbl *cmdtp, int flag,
ret = xilinx_pm_request(PM_SECURE_SHA, upper_32_bits((ulong)srcaddr),
lower_32_bits((ulong)srcaddr),
srclen, ZYNQMP_SHA3_UPDATE, ret_payload);
srclen, ZYNQMP_SHA3_UPDATE, 0, 0, ret_payload);
if (ret || ret_payload[1]) {
printf("Failed: SHA UPDATE status:0x%x, errcode:0x%x\n",
ret, ret_payload[1]);
@@ -328,7 +328,7 @@ static int do_zynqmp_sha3(struct cmd_tbl *cmdtp, int flag,
ret = xilinx_pm_request(PM_SECURE_SHA, upper_32_bits((ulong)hashaddr),
lower_32_bits((ulong)hashaddr),
ZYNQMP_SHA3_SIZE, ZYNQMP_SHA3_FINAL,
ret_payload);
0, 0, ret_payload);
if (ret || ret_payload[1]) {
printf("Failed: SHA FINAL status:0x%x, errcode:0x%x\n",
ret, ret_payload[1]);

2
board/xilinx/zynqmp/zynqmp.c
View File

@@ -293,7 +293,7 @@ void reset_cpu(void)
* will send command over IPI and requires pmufw to be present.
*/
xilinx_pm_request(PM_RESET_ASSERT, ZYNQMP_PM_RESET_SOFT,
PM_RESET_ACTION_ASSERT, 0, 0, NULL);
PM_RESET_ACTION_ASSERT, 0, 0, 0, 0, NULL);
}
#endif

25
drivers/clk/clk_versal.c
View File

@@ -131,7 +131,7 @@ static int versal_pm_query_legacy(struct versal_pm_query_data qdata,
int ret;
ret = smc_call_handler(PM_QUERY_DATA, qdata.qid, qdata.arg1, qdata.arg2,
qdata.arg3, ret_payload);
qdata.arg3, 0, 0, ret_payload);
return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : ret;
}
@@ -350,7 +350,8 @@ static u32 versal_clock_get_div(u32 clk_id)
u32 ret_payload[PAYLOAD_ARG_CNT];
u32 div;
xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, 0, 0,
ret_payload);
div = ret_payload[1];
return div;
@@ -360,7 +361,8 @@ static u32 versal_clock_set_div(u32 clk_id, u32 div)
{
u32 ret_payload[PAYLOAD_ARG_CNT];
xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, 0, 0,
ret_payload);
return div;
}
@@ -418,7 +420,7 @@ static u32 versal_clock_get_parentid(u32 clk_id)
if (versal_clock_mux(clk_id)) {
xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
ret_payload);
0, 0, ret_payload);
parent_id = ret_payload[1];
}
@@ -436,7 +438,8 @@ static u64 versal_clock_get_pll_rate(u32 clk_id)
u32 parent_rate, parent_id, parent_ref_clk_id;
u32 id = clk_id & 0xFFF;
xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, 0, 0,
ret_payload);
res = ret_payload[1];
if (!res) {
printf("0%x PLL not enabled\n", clk_id);
@@ -447,9 +450,11 @@ static u64 versal_clock_get_pll_rate(u32 clk_id)
parent_ref_clk_id = versal_clock_get_parentid(parent_id);
parent_rate = versal_clock_get_ref_rate(parent_ref_clk_id);
xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, 0, 0,
ret_payload);
fbdiv = ret_payload[1];
xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, 0, 0,
ret_payload);
frac = ret_payload[1];
freq = (fbdiv * parent_rate) >> (1 << frac);
@@ -765,8 +770,10 @@ static int versal_clk_enable(struct clk *clk)
clk_id = priv->clk[clk->id].clk_id;
if (versal_clock_gate(clk_id))
return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
if (versal_clock_gate(clk_id)) {
return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0,
0, 0, NULL);
}
return 0;
}

36
drivers/firmware/firmware-zynqmp.c
View File

@@ -3,6 +3,7 @@
* Xilinx Zynq MPSoC Firmware driver
*
* Copyright (C) 2018-2019 Xilinx, Inc.
* Copyright (C) 2022 - 2025, Advanced Micro Devices, Inc.
*/
#include <asm/arch/hardware.h>
@@ -158,7 +159,7 @@ unsigned int zynqmp_firmware_version(void)
if (pm_api_version == ZYNQMP_PM_VERSION_INVALID) {
ret = xilinx_pm_request(PM_GET_API_VERSION, 0, 0, 0, 0,
ret_payload);
0, 0, ret_payload);
if (ret)
panic("PMUFW is not found - Please load it!\n");
@@ -202,7 +203,7 @@ int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config, u32 value
int ret;
ret = xilinx_pm_request(PM_IOCTL, node, IOCTL_SET_GEM_CONFIG,
config, value, NULL);
config, value, 0, 0, NULL);
if (ret)
printf("%s: node %d: set_gem_config %d failed\n",
__func__, node, config);
@@ -215,7 +216,7 @@ int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value)
int ret;
ret = xilinx_pm_request(PM_IOCTL, node, IOCTL_SET_SD_CONFIG,
config, value, NULL);
config, value, 0, 0, NULL);
if (ret)
printf("%s: node %d: set_sd_config %d failed\n",
__func__, node, config);
@@ -236,7 +237,7 @@ u32 zynqmp_pm_get_bootmode_reg(void)
}
ret = xilinx_pm_request(PM_IOCTL, CRP_BOOT_MODE_REG_NODE, IOCTL_READ_REG,
CRP_BOOT_MODE_REG_OFFSET, 0, ret_payload);
CRP_BOOT_MODE_REG_OFFSET, 0, 0, 0, ret_payload);
if (ret) {
printf("%s: node 0x%x: get_bootmode 0x%x failed\n",
__func__, CRP_BOOT_MODE_REG_NODE, CRP_BOOT_MODE_REG_OFFSET);
@@ -259,7 +260,8 @@ u32 zynqmp_pm_get_pmc_multi_boot_reg(void)
}
ret = xilinx_pm_request(PM_IOCTL, PM_REG_PMC_GLOBAL_NODE, IOCTL_READ_REG,
PMC_MULTI_BOOT_MODE_REG_OFFSET, 0, ret_payload);
PMC_MULTI_BOOT_MODE_REG_OFFSET, 0, 0, 0,
ret_payload);
if (ret) {
printf("%s: node 0x%x: get_bootmode 0x%x failed\n",
__func__, PM_REG_PMC_GLOBAL_NODE, PMC_MULTI_BOOT_MODE_REG_OFFSET);
@@ -276,7 +278,7 @@ int zynqmp_pm_feature(const u32 api_id)
/* Check feature check API version */
ret = xilinx_pm_request(PM_FEATURE_CHECK, api_id, 0, 0, 0,
ret_payload);
0, 0, ret_payload);
if (ret)
return ret;
@@ -296,7 +298,7 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
/* Check feature check API version */
ret = xilinx_pm_request(PM_FEATURE_CHECK, PM_FEATURE_CHECK, 0, 0, 0,
ret_payload);
0, 0, ret_payload);
if (ret)
return ret;
@@ -308,7 +310,7 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id)
*/
ret = xilinx_pm_request(PM_FEATURE_CHECK, api_id, 0, 0, 0,
ret_payload);
0, 0, ret_payload);
if (ret)
return ret;
@@ -340,7 +342,7 @@ int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
flush_dcache_range((ulong)cfg_obj, (ulong)(cfg_obj + size));
err = xilinx_pm_request(PM_SET_CONFIGURATION, (u32)(u64)cfg_obj, 0, 0,
0, ret_payload);
0, 0, 0, ret_payload);
if (err == XST_PM_NO_ACCESS) {
return -EACCES;
}
@@ -425,13 +427,14 @@ U_BOOT_DRIVER(zynqmp_power) = {
smc_call_handler_t __data smc_call_handler;
static int smc_call_legacy(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
u32 arg3, u32 *ret_payload)
u32 arg3, u32 arg4, u32 arg5, u32 *ret_payload)
{
struct pt_regs regs;
regs.regs[0] = PM_SIP_SVC | api_id;
regs.regs[1] = ((u64)arg1 << 32) | arg0;
regs.regs[2] = ((u64)arg3 << 32) | arg2;
regs.regs[3] = arg4;
smc_call(&regs);
@@ -441,16 +444,18 @@ static int smc_call_legacy(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
ret_payload[2] = (u32)regs.regs[1];
ret_payload[3] = upper_32_bits(regs.regs[1]);
ret_payload[4] = (u32)regs.regs[2];
ret_payload[5] = upper_32_bits((u32)regs.regs[2]);
ret_payload[6] = (u32)regs.regs[3];
}
return (ret_payload) ? ret_payload[0] : 0;
}
int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
u32 arg3, u32 *ret_payload)
u32 arg3, u32 arg4, u32 arg5, u32 *ret_payload)
{
debug("%s at EL%d, API ID: 0x%0x, 0x%0x, 0x%0x, 0x%0x, 0x%0x\n",
__func__, current_el(), api_id, arg0, arg1, arg2, arg3);
debug("%s at EL%d, API ID: 0x%0x, 0x%0x, 0x%0x, 0x%0x, 0x%0x, 0x%0x, 0x%0x\n",
__func__, current_el(), api_id, arg0, arg1, arg2, arg3, arg4, arg5);
if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) {
#if defined(CONFIG_ZYNQMP_IPI)
@@ -459,7 +464,7 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
* is capable to handle PMUFW_PAYLOAD_ARG_CNT bytes but the
* firmware API is limited by the SMC call size
*/
u32 regs[] = {api_id, arg0, arg1, arg2, arg3};
u32 regs[] = {api_id, arg0, arg1, arg2, arg3, arg4, arg5};
int ret;
if (api_id == PM_FPGA_LOAD) {
@@ -481,7 +486,8 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
#endif
}
return smc_call_handler(api_id, arg0, arg1, arg2, arg3, ret_payload);
return smc_call_handler(api_id, arg0, arg1, arg2, arg3, arg4,
arg5, ret_payload);
}
static const struct udevice_id zynqmp_firmware_ids[] = {

5
drivers/fpga/versalpl.c
View File

@@ -40,13 +40,12 @@ static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
buf_lo = lower_32_bits(bin_buf);
buf_hi = upper_32_bits(bin_buf);
if (desc->family == xilinx_versal2) {
ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_hi,
buf_lo, 0, ret_payload);
buf_lo, 0, 0, 0, ret_payload);
} else {
ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
buf_hi, 0, ret_payload);
buf_hi, 0, 0, 0, ret_payload);
}
if (ret)

8
drivers/fpga/zynqmppl.c
View File

@@ -291,7 +291,7 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize,
buf_hi = upper_32_bits(bin_buf);
ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, buf_hi,
bsize_req, bstype, ret_payload);
bsize_req, bstype, 0, 0, ret_payload);
if (ret)
printf("PL FPGA LOAD failed with err: 0x%08x\n", ret);
@@ -335,11 +335,11 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize,
ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
buf_hi,
(u32)(uintptr_t)fpga_sec_info->userkey_addr,
flag, ret_payload);
flag, 0, 0, ret_payload);
else
ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo,
buf_hi, (u32)bsize,
flag, ret_payload);
flag, 0, 0, ret_payload);
if (ret)
puts("PL FPGA LOAD fail\n");
@@ -356,7 +356,7 @@ static int zynqmp_pcap_info(xilinx_desc *desc)
u32 ret_payload[PAYLOAD_ARG_CNT];
ret = xilinx_pm_request(PM_FPGA_GET_STATUS, 0, 0, 0,
0, ret_payload);
0, 0, 0, ret_payload);
if (!ret)
printf("PCAP status\t0x%x\n", ret_payload[1]);

4
drivers/gpio/zynqmp_gpio_modepin.c
View File

@@ -23,14 +23,14 @@
static int get_gpio_modepin(u32 *ret_payload)
{
return xilinx_pm_request(PM_MMIO_READ, ZYNQMP_CRL_APB_BOOT_PIN_CTRL,
0, 0, 0, ret_payload);
0, 0, 0, 0, 0, ret_payload);
}
static int set_gpio_modepin(int val)
{
return xilinx_pm_request(PM_MMIO_WRITE, ZYNQMP_CRL_APB_BOOT_PIN_CTRL,
ZYNQMP_CRL_APB_BOOTPIN_CTRL_MASK,
val, 0, NULL);
val, 0, 0, 0, NULL);
}
static int modepin_gpio_direction_input(struct udevice *dev,

13
drivers/mmc/zynq_sdhci.c
View File

@@ -125,7 +125,7 @@ __weak int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value)
}
__weak int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
u32 arg3, u32 *ret_payload)
u32 arg3, u32 arg4, u32 arg5, u32 *ret_payload)
{
return 0;
}
@@ -331,7 +331,8 @@ static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay)
} else {
return xilinx_pm_request(PM_IOCTL, node_id,
IOCTL_SET_SD_TAPDELAY,
PM_TAPDELAY_INPUT, itap_delay, NULL);
PM_TAPDELAY_INPUT, itap_delay, 0, 0,
NULL);
}
return 0;
@@ -350,7 +351,8 @@ static inline int arasan_zynqmp_set_out_tapdelay(u32 node_id, u32 otap_delay)
} else {
return xilinx_pm_request(PM_IOCTL, node_id,
IOCTL_SET_SD_TAPDELAY,
PM_TAPDELAY_OUTPUT, otap_delay, NULL);
PM_TAPDELAY_OUTPUT, otap_delay, 0, 0,
NULL);
}
}
@@ -367,7 +369,8 @@ static inline int zynqmp_dll_reset(u32 node_id, u32 type)
SD1_DLL_RST : 0);
} else {
return xilinx_pm_request(PM_IOCTL, node_id,
IOCTL_SD_DLL_RESET, type, 0, NULL);
IOCTL_SD_DLL_RESET, type, 0, 0, 0,
NULL);
}
}
@@ -1021,7 +1024,7 @@ static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv,
ret = xilinx_pm_request(PM_REQUEST_NODE, priv->node_id,
ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
ZYNQMP_PM_REQUEST_ACK_NO, NULL);
ZYNQMP_PM_REQUEST_ACK_NO, 0, 0, NULL);
if (ret) {
dev_err(dev, "Request node failed for %d\n", priv->node_id);
return ret;

24
drivers/pinctrl/pinctrl-zynqmp.c
View File

@@ -127,7 +127,8 @@ static int zynqmp_pm_query_data(enum pm_query_id qid, u32 arg1, u32 arg2, u32 *o
int ret;
u32 ret_payload[PAYLOAD_ARG_CNT];
ret = xilinx_pm_request(PM_QUERY_DATA, qid, arg1, arg2, 0, ret_payload);
ret = xilinx_pm_request(PM_QUERY_DATA, qid, arg1, arg2, 0, 0,
0, ret_payload);
if (ret)
return ret;
@@ -142,7 +143,8 @@ static int zynqmp_pm_pinctrl_get_config(const u32 pin, const u32 param, u32 *val
u32 ret_payload[PAYLOAD_ARG_CNT];
/* Get config for the pin */
ret = xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_GET, pin, param, 0, 0, ret_payload);
ret = xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_GET, pin, param, 0, 0, 0,
0, ret_payload);
if (ret) {
printf("%s failed\n", __func__);
return ret;
@@ -164,14 +166,15 @@ static int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, u32 valu
}
/* Request the pin first */
ret = xilinx_pm_request(PM_PINCTRL_REQUEST, pin, 0, 0, 0, NULL);
ret = xilinx_pm_request(PM_PINCTRL_REQUEST, pin, 0, 0, 0, 0, 0, NULL);
if (ret) {
printf("%s: pin request failed\n", __func__);
return ret;
}
/* Set config for the pin */
ret = xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, pin, param, value, 0, NULL);
ret = xilinx_pm_request(PM_PINCTRL_CONFIG_PARAM_SET, pin, param, value,
0, 0, 0, NULL);
if (ret) {
printf("%s failed\n", __func__);
return ret;
@@ -186,7 +189,7 @@ static int zynqmp_pinctrl_get_function_groups(u32 fid, u32 index, u16 *groups)
u32 ret_payload[PAYLOAD_ARG_CNT];
ret = xilinx_pm_request(PM_QUERY_DATA, PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
fid, index, 0, ret_payload);
fid, index, 0, 0, 0, ret_payload);
if (ret) {
printf("%s failed\n", __func__);
return ret;
@@ -242,7 +245,7 @@ static int zynqmp_pinctrl_get_pin_groups(u32 pin, u32 index, u16 *groups)
u32 ret_payload[PAYLOAD_ARG_CNT];
ret = xilinx_pm_request(PM_QUERY_DATA, PM_QID_PINCTRL_GET_PIN_GROUPS,
pin, index, 0, ret_payload);
pin, index, 0, 0, 0, ret_payload);
if (ret) {
printf("%s failed to get pin groups\n", __func__);
return ret;
@@ -313,13 +316,13 @@ static int zynqmp_pinctrl_probe(struct udevice *dev)
for (i = 0; i < priv->nfuncs; i++) {
/* Get function name for the function and fill */
xilinx_pm_request(PM_QUERY_DATA, PM_QID_PINCTRL_GET_FUNCTION_NAME,
i, 0, 0, ret_payload);
i, 0, 0, 0, 0, ret_payload);
memcpy((void *)priv->funcs[i].name, ret_payload, MAX_FUNC_NAME_LEN);
/* And fill number of groups available for certain function */
xilinx_pm_request(PM_QUERY_DATA, PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
i, 0, 0, ret_payload);
i, 0, 0, 0, 0, ret_payload);
priv->funcs[i].ngroups = ret_payload[1];
priv->ngroups += priv->funcs[i].ngroups;
@@ -370,7 +373,8 @@ static int zynqmp_pinmux_set(struct udevice *dev, unsigned int selector,
int ret;
/* Request the pin first */
ret = xilinx_pm_request(PM_PINCTRL_REQUEST, selector, 0, 0, 0, NULL);
ret = xilinx_pm_request(PM_PINCTRL_REQUEST, selector, 0, 0, 0, 0,
0, NULL);
if (ret) {
printf("%s: pin request failed\n", __func__);
return ret;
@@ -378,7 +382,7 @@ static int zynqmp_pinmux_set(struct udevice *dev, unsigned int selector,
/* Set the pin function */
ret = xilinx_pm_request(PM_PINCTRL_SET_FUNCTION, selector, func_selector,
0, 0, NULL);
0, 0, 0, 0, NULL);
if (ret) {
printf("%s: Failed to set pinmux function\n", __func__);
return ret;

2
drivers/power/domain/zynqmp-power-domain.c
View File

@@ -17,7 +17,7 @@ static int zynqmp_pm_request_node(const u32 node, const u32 capabilities,
const u32 qos, const enum zynqmp_pm_request_ack ack)
{
return xilinx_pm_request(PM_REQUEST_NODE, node, capabilities,
qos, ack, NULL);
qos, ack, 0, 0, NULL);
}
static int zynqmp_power_domain_request(struct power_domain *power_domain)

2
drivers/reset/reset-zynqmp.c
View File

@@ -22,7 +22,7 @@ static int zynqmp_pm_reset_assert(const u32 reset,
const enum zynqmp_pm_reset_action assert_flag)
{
return xilinx_pm_request(PM_RESET_ASSERT, reset, assert_flag, 0, 0,
NULL);
0, 0, NULL);
}
static int zynqmp_reset_assert(struct reset_ctl *rst)

2
drivers/soc/soc_amd_versal2.c
View File

@@ -55,7 +55,7 @@ static int soc_amd_versal2_probe(struct udevice *dev)
if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) {
ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0,
ret_payload);
0, 0, ret_payload);
if (ret)
return ret;
} else {

2
drivers/soc/soc_xilinx_versal.c
View File

@@ -51,7 +51,7 @@ static int soc_xilinx_versal_probe(struct udevice *dev)
if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) {
ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0,
ret_payload);
0, 0, ret_payload);
if (ret)
return ret;
} else {

2
drivers/soc/soc_xilinx_versal_net.c
View File

@@ -53,7 +53,7 @@ static int soc_xilinx_versal_net_probe(struct udevice *dev)
if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) {
ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0,
ret_payload);
0, 0, ret_payload);
if (ret)
return ret;
} else {

2
drivers/soc/soc_xilinx_zynqmp.c
View File

@@ -362,7 +362,7 @@ static int soc_xilinx_zynqmp_probe(struct udevice *dev)
ret = zynqmp_mmio_read(ZYNQMP_PS_VERSION, &ret_payload[2]);
else
ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0,
ret_payload);
0, 0, ret_payload);
if (ret < 0)
return ret;

4
drivers/spi/cadence_ospi_versal.c
View File

@@ -199,12 +199,12 @@ void cadence_qspi_apb_enable_linear_mode(bool enable)
/* ahb read mode */
xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI,
IOCTL_OSPI_MUX_SELECT,
PM_OSPI_MUX_SEL_LINEAR, 0, NULL);
PM_OSPI_MUX_SEL_LINEAR, 0, 0, 0, NULL);
else
/* DMA mode */
xilinx_pm_request(PM_IOCTL, PM_DEV_OSPI,
IOCTL_OSPI_MUX_SELECT,
PM_OSPI_MUX_SEL_DMA, 0, NULL);
PM_OSPI_MUX_SEL_DMA, 0, 0, 0, NULL);
} else {
if (enable)
writel(readl(VERSAL_AXI_MUX_SEL) |

2
drivers/spi/cadence_qspi.c
View File

@@ -230,7 +230,7 @@ static int cadence_spi_probe(struct udevice *bus)
if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE))
xilinx_pm_request(PM_REQUEST_NODE, PM_DEV_OSPI,
ZYNQMP_PM_CAPABILITY_ACCESS, ZYNQMP_PM_MAX_QOS,
ZYNQMP_PM_REQUEST_ACK_NO, NULL);
ZYNQMP_PM_REQUEST_ACK_NO, 0, 0, NULL);
if (priv->ref_clk_hz == 0) {
ret = clk_get_by_index(bus, 0, &clk);

8
include/zynqmp_firmware.h
View File

@@ -440,18 +440,18 @@ enum pm_gem_config_type {
/*
* Return payload size
* Not every firmware call expects the same amount of return bytes, however the
* firmware driver always copies 5 bytes from RX buffer to the ret_payload
* firmware driver always copies 7 words from RX buffer to the ret_payload
* buffer. Therefore allocating with this defined value is recommended to avoid
* overflows.
*/
#define PAYLOAD_ARG_CNT 5U
#define PAYLOAD_ARG_CNT 7U
unsigned int zynqmp_firmware_version(void);
int zynqmp_pmufw_node(u32 id);
int zynqmp_pmufw_config_close(void);
int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
u32 arg3, u32 *ret_payload);
u32 arg3, u32 arg4, u32 arg5, u32 *ret_payload);
int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
u32 value);
@@ -517,7 +517,7 @@ struct zynqmp_ipi_msg {
#define __data __section(".data")
typedef int (*smc_call_handler_t)(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
u32 arg3, u32 *ret_payload);
u32 arg3, u32 arg4, u32 arg5, u32 *ret_payload);
extern smc_call_handler_t __data smc_call_handler;