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Merge tag 'xilinx-for-v2026.04-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Browse Source 
AMD/Xilinx/FPGA changes for v2026.04-rc1 v2

microblaze:
- Fix spl_boot_list order

versal2:
- Fix EMMC distro boot setup
- Align distro boot variables with memory layout

zynqmp-phy:
- Sync with Linux kernel driver

zynqmp:
- Add verify_auth command
- DT sync
- Add placing variables to FAT/EXT4
- Enable PCIe driver by default

pcie - xilinx-nwl:
- Fix Link down crash

ufs:
- Align clock/reset with DT binding

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# =AkKK
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 19 Jan 2026 02:22:55 AM CST
# gpg:                using EDDSA key 97022C40ACF6D6A516A7596FAB07FEF04EF511F5
# gpg: Can't check signature: No public key
This commit is contained in:
Tom Rini
2026-01-19 13:08:48 -06:00
parent 8f16767dcc 8a532b5a22
commit 55ca2110d7
42 changed files with 249 additions and 259 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/dts/zynqmp-clk-ccf.dtsi
View File

@@ -14,7 +14,7 @@
bootph-all;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <33333333>;
clock-frequency = <33333000>;
clock-output-names = "pss_ref_clk";
};

8
arch/arm/dts/zynqmp-dlc21-revA.dts
View File

@@ -176,12 +176,12 @@
};
&dwc3_1 {
/delete-property/ phy-names ;
/delete-property/ phys ;
/delete-property/ phy-names;
/delete-property/ phys;
dr_mode = "host";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk ;
snps,dis_u3_susphy_quirk ;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
status = "okay";
};

4
arch/arm/dts/zynqmp-e-a2197-00-revA.dts
View File

@@ -107,7 +107,8 @@
};
ina226-vcc-1v2-ddr4 {
compatible = "iio-hwmon";
io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;
io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>,
<&vcc_1v2_ddr4 3>;
};
ina226-vcc-1v1-lp4 {
compatible = "iio-hwmon";
@@ -465,7 +466,6 @@
clock-output-names = "si570_user1";
silabs,skip-recall;
};
};
i2c@7 { /* USER_SI570_2 */
#address-cells = <1>;

2
arch/arm/dts/zynqmp-g-a2197-00-revA.dts
View File

@@ -89,7 +89,7 @@
phy0: ethernet-phy@0 { /* marwell m88e1512 */
reg = <0>;
reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
};
};
};

13
arch/arm/dts/zynqmp-m-a2197-01-revA.dts
View File

@@ -61,7 +61,8 @@
};
ina226-vdd1-1v8-lp4 {
compatible = "iio-hwmon";
io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>,
<&vdd1_1v8_lp4 3>;
};
ina226-vcc0v6-lp4 {
compatible = "iio-hwmon";
@@ -120,7 +121,7 @@
reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
phy0: ethernet-phy@0 { /* marwell m88e1512 - SGMII */
reg = <0>;
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
};
};
};
@@ -483,10 +484,10 @@
};
&dwc3_1 {
/delete-property/ phy-names ;
/delete-property/ phys ;
/delete-property/ phy-names;
/delete-property/ phys;
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk ;
snps,dis_u3_susphy_quirk ;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
status = "disabled";
};

11
arch/arm/dts/zynqmp-m-a2197-02-revA.dts
View File

@@ -61,7 +61,8 @@
};
ina226-vdd1-1v8-lp4 {
compatible = "iio-hwmon";
io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>,
<&vdd1_1v8_lp4 3>;
};
};
@@ -485,10 +486,10 @@
};
&dwc3_1 {
/delete-property/ phy-names ;
/delete-property/ phys ;
/delete-property/ phy-names;
/delete-property/ phys;
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk ;
snps,dis_u3_susphy_quirk ;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
status = "disabled";
};

11
arch/arm/dts/zynqmp-m-a2197-03-revA.dts
View File

@@ -61,7 +61,8 @@
};
ina226-vdd1-1v8-lp4 {
compatible = "iio-hwmon";
io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>;
io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>,
<&vdd1_1v8_lp4 3>;
};
};
@@ -479,10 +480,10 @@
};
&dwc3_1 {
/delete-property/ phy-names ;
/delete-property/ phys ;
/delete-property/ phy-names;
/delete-property/ phys;
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk ;
snps,dis_u3_susphy_quirk ;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
status = "disabled";
};

8
arch/arm/dts/zynqmp-p-a2197-00-revA.dts
View File

@@ -558,12 +558,12 @@
};
&dwc3_1 {
/delete-property/ phy-names ;
/delete-property/ phys ;
/delete-property/ phy-names;
/delete-property/ phys;
dr_mode = "host";
maximum-speed = "high-speed";
snps,dis_u2_susphy_quirk ;
snps,dis_u3_susphy_quirk ;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
status = "okay";
};

20
arch/arm/dts/zynqmp-sc-revB.dts
View File

@@ -222,35 +222,35 @@
};
partition@140000 {
label = "Open_1";
reg = <0x140000 0xC0000>; /* 768KB */
reg = <0x140000 0xc0000>; /* 768KB */
};
partition@200000 {
label = "Image A (FSBL, PMU, ATF, U-Boot)";
reg = <0x200000 0xD00000>; /* 13MB */
reg = <0x200000 0xd00000>; /* 13MB */
};
partition@f00000 {
label = "ImgSel Image A Catch";
reg = <0xF00000 0x80000>; /* 512KB */
reg = <0xf00000 0x80000>; /* 512KB */
read-only;
lock;
};
partition@f80000 {
label = "Image B (FSBL, PMU, ATF, U-Boot)";
reg = <0xF80000 0xD00000>; /* 13MB */
reg = <0xf80000 0xd00000>; /* 13MB */
};
partition@1c80000 {
label = "ImgSel Image B Catch";
reg = <0x1C80000 0x80000>; /* 512KB */
reg = <0x1c80000 0x80000>; /* 512KB */
read-only;
lock;
};
partition@1d00000 {
label = "Open_2";
reg = <0x1D00000 0x100000>; /* 1MB */
reg = <0x1d00000 0x100000>; /* 1MB */
};
partition@1e00000 {
label = "Recovery Image";
reg = <0x1E00000 0x200000>; /* 2MB */
reg = <0x1e00000 0x200000>; /* 2MB */
read-only;
lock;
};
@@ -278,9 +278,9 @@
label = "Secure OS Storage";
reg = <0x2280000 0x20000>; /* 128KB */
};
partition@22A0000 {
partition@22a0000 {
label = "User";
reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
reg = <0x22a0000 0x1d60000>; /* 29.375 MB */
};
};
};
@@ -409,7 +409,7 @@
conf-tx {
pins = "MIO38", "MIO39", "MIO40",
"MIO41", "MIO42", "MIO43";
"MIO41", "MIO42", "MIO43";
bias-disable;
low-power-enable;
};

6
arch/arm/dts/zynqmp-sck-kd-g-revA.dtso
View File

@@ -26,11 +26,6 @@
ethernet0 = "/axi/ethernet@ff0c0000"; /* &gem1 */
};
ina260-u3 {
compatible = "iio-hwmon";
io-channels = <&u3 0>, <&u3 1>, <&u3 2>;
};
clk_26: clock2 { /* u17 - USB */
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -67,7 +62,6 @@
u3: ina260@40 { /* u3 */
compatible = "ti,ina260";
#io-channel-cells = <1>;
label = "ina260-u14";
reg = <0x40>;
};

6
arch/arm/dts/zynqmp-sck-kr-g-revA.dtso
View File

@@ -25,11 +25,6 @@
ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */
};
ina260-u14 {
compatible = "iio-hwmon";
io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
};
clk_27: clock0 { /* u86 - DP */
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -95,7 +90,6 @@
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
#io-channel-cells = <1>;
label = "ina260-u14";
reg = <0x40>;
};

6
arch/arm/dts/zynqmp-sck-kr-g-revB.dtso
View File

@@ -25,11 +25,6 @@
ethernet1 = "/axi/ethernet@ff0c0000"; /* &gem1 */
};
ina260-u14 {
compatible = "iio-hwmon";
io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
};
clk_125: clock0 { /* u87 - GEM0/1 */
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -96,7 +91,6 @@
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
#io-channel-cells = <1>;
label = "ina260-u14";
reg = <0x40>;
};

6
arch/arm/dts/zynqmp-sck-kv-g-revA.dtso
View File

@@ -32,11 +32,6 @@
ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */
};
ina260-u14 {
compatible = "iio-hwmon";
io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
};
si5332_0: si5332-0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -96,7 +91,6 @@
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
#io-channel-cells = <1>;
label = "ina260-u14";
reg = <0x40>;
};

6
arch/arm/dts/zynqmp-sck-kv-g-revB.dtso
View File

@@ -27,11 +27,6 @@
ethernet0 = "/axi/ethernet@ff0e0000"; /* &gem3 */
};
ina260-u14 {
compatible = "iio-hwmon";
io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
};
si5332_0: si5332-0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -92,7 +87,6 @@
u14: ina260@40 { /* u14 */
compatible = "ti,ina260";
#io-channel-cells = <1>;
label = "ina260-u14";
reg = <0x40>;
};

1
arch/arm/dts/zynqmp-vpk120-revA.dts
View File

@@ -375,7 +375,6 @@
clock-frequency = <100000000>;
clock-output-names = "fmc_si570";
};
};
/* 7 unused */
};

2
arch/arm/dts/zynqmp-zc1232-revA.dts
View File

@@ -61,7 +61,7 @@
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
reg = <0x620000 0x5e0000>;
};
};
};

2
arch/arm/dts/zynqmp-zc1254-revA.dts
View File

@@ -62,7 +62,7 @@
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
reg = <0x620000 0x5e0000>;
};
};
};

2
arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
View File

@@ -378,7 +378,7 @@
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
reg = <0x620000 0x5e0000>;
};
};
};

8
arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts
View File

@@ -156,7 +156,7 @@
};
partition@3 { /* for testing purpose */
label = "nand-rootfs";
reg = <0x0 0x1C00000 0x1400000>;
reg = <0x0 0x1c00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand-bitstream";
@@ -164,7 +164,7 @@
};
partition@5 { /* for testing purpose */
label = "nand-misc";
reg = <0x0 0x3400000 0xFCC00000>;
reg = <0x0 0x3400000 0xfcc00000>;
};
};
nand@1 {
@@ -192,7 +192,7 @@
};
partition@3 { /* for testing purpose */
label = "nand1-rootfs";
reg = <0x0 0x1C00000 0x1400000>;
reg = <0x0 0x1c00000 0x1400000>;
};
partition@4 { /* for testing purpose */
label = "nand1-bitstream";
@@ -200,7 +200,7 @@
};
partition@5 { /* for testing purpose */
label = "nand1-misc";
reg = <0x0 0x3400000 0xFCC00000>;
reg = <0x0 0x3400000 0xfcc00000>;
};
};
};

2
arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
View File

@@ -194,7 +194,7 @@
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
reg = <0x620000 0x5e0000>;
};
};
};

2
arch/arm/dts/zynqmp-zcu102-revA.dts
View File

@@ -1008,7 +1008,7 @@
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
reg = <0x620000 0x5e0000>;
};
};
};

2
arch/arm/dts/zynqmp-zcu104-revA.dts
View File

@@ -473,7 +473,7 @@
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
reg = <0x620000 0x5e0000>;
};
};
};

2
arch/arm/dts/zynqmp-zcu104-revC.dts
View File

@@ -485,7 +485,7 @@
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
reg = <0x620000 0x5e0000>;
};
};
};

2
arch/arm/dts/zynqmp-zcu106-revA.dts
View File

@@ -1002,7 +1002,7 @@
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
reg = <0x620000 0x5e0000>;
};
};
};

2
arch/arm/dts/zynqmp-zcu111-revA.dts
View File

@@ -825,7 +825,7 @@
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
reg = <0x620000 0x5e0000>;
};
};
};

2
arch/arm/dts/zynqmp-zcu1275-revA.dts
View File

@@ -66,7 +66,7 @@
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
reg = <0x620000 0x5e0000>;
};
};
};

2
arch/arm/dts/zynqmp-zcu1275-revB.dts
View File

@@ -93,7 +93,7 @@
};
partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
reg = <0x620000 0x5e0000>;
};
};
};

2
arch/arm/dts/zynqmp-zcu1285-revA.dts
View File

@@ -36,7 +36,6 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
&dcc {
@@ -46,7 +45,6 @@
&i2c0 {
status = "okay";
clock-frequency = <400000>;
};
&gem1 {

22
arch/arm/dts/zynqmp-zcu208-revA.dts
View File

@@ -70,7 +70,8 @@
};
ina226-vccint-io-bram {
compatible = "iio-hwmon";
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>,
<&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
};
ina226-vcc1v8 {
compatible = "iio-hwmon";
@@ -106,7 +107,8 @@
};
ina226-dac-avccaux {
compatible = "iio-hwmon";
io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>,
<&dac_avccaux 3>;
};
ina226-adc-avcc {
compatible = "iio-hwmon";
@@ -114,7 +116,8 @@
};
ina226-adc-avccaux {
compatible = "iio-hwmon";
io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>,
<&adc_avccaux 3>;
};
ina226-dac-avcc {
compatible = "iio-hwmon";
@@ -379,7 +382,6 @@
reg = <0x45>; /* i2c addr 0x15 */
};
/* J21 header too */
};
i2c@3 {
#address-cells = <1>;
@@ -671,13 +673,13 @@
status = "okay";
/* SATA OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0e>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4a 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96a4 0x3ffc>;
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0e>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4a 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96a4 0x3ffc>;
phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};

22
arch/arm/dts/zynqmp-zcu216-revA.dts
View File

@@ -70,7 +70,8 @@
};
ina226-vccint-io-bram {
compatible = "iio-hwmon";
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>,
<&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
};
ina226-vcc1v8 {
compatible = "iio-hwmon";
@@ -106,7 +107,8 @@
};
ina226-dac-avccaux {
compatible = "iio-hwmon";
io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>,
<&dac_avccaux 3>;
};
ina226-adc-avcc {
compatible = "iio-hwmon";
@@ -114,7 +116,8 @@
};
ina226-adc-avccaux {
compatible = "iio-hwmon";
io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>,
<&adc_avccaux 3>;
};
ina226-dac-avcc {
compatible = "iio-hwmon";
@@ -389,7 +392,6 @@
reg = <0x45>; /* i2c addr 0x15 */
};
/* J21 header too */
};
i2c@3 {
#address-cells = <1>;
@@ -674,13 +676,13 @@
status = "okay";
/* SATA OOB timing settings */
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0e>;
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4a 0x06>;
ceva,p0-retry-params = /bits/ 16 <0x96a4 0x3ffc>;
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0e>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4a 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96a4 0x3ffc>;
phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};

18
arch/arm/dts/zynqmp-zcu670-revA.dts
View File

@@ -73,7 +73,8 @@
};
ina226-vccint-io-bram {
compatible = "iio-hwmon";
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>,
<&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
};
ina226-vcc1v8 {
compatible = "iio-hwmon";
@@ -109,7 +110,8 @@
};
ina226-dac-avccaux {
compatible = "iio-hwmon";
io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>,
<&dac_avccaux 3>;
};
ina226-adc-avcc {
compatible = "iio-hwmon";
@@ -117,7 +119,8 @@
};
ina226-adc-avccaux {
compatible = "iio-hwmon";
io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>,
<&adc_avccaux 3>;
};
ina226-dac-avcc {
compatible = "iio-hwmon";
@@ -388,7 +391,6 @@
reg = <0x45>; /* i2c addr 0x15 */
};
/* J21 header too */
};
i2c@3 {
#address-cells = <1>;
@@ -437,9 +439,11 @@
#size-cells = <0>;
reg = <1>;
/* SI5381 - u43 */
/* si5381: clock-generator@68 {
reg = <0x68>;
};*/
/*
* si5381: clock-generator@68 {
* reg = <0x68>;
* };
*/
};
i2c_si570_user_c0: i2c@2 {
#address-cells = <1>;

18
arch/arm/dts/zynqmp-zcu670-revB.dts
View File

@@ -73,7 +73,8 @@
};
ina226-vccint-io-bram {
compatible = "iio-hwmon";
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>,
<&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
};
ina226-vcc1v8 {
compatible = "iio-hwmon";
@@ -109,7 +110,8 @@
};
ina226-dac-avccaux {
compatible = "iio-hwmon";
io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>,
<&dac_avccaux 3>;
};
ina226-adc-avcc {
compatible = "iio-hwmon";
@@ -117,7 +119,8 @@
};
ina226-adc-avccaux {
compatible = "iio-hwmon";
io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>,
<&adc_avccaux 3>;
};
ina226-dac-avcc {
compatible = "iio-hwmon";
@@ -388,7 +391,6 @@
reg = <0x45>; /* i2c addr 0x15 */
};
/* J21 header too */
};
i2c@3 {
#address-cells = <1>;
@@ -437,9 +439,11 @@
#size-cells = <0>;
reg = <1>;
/* SI5381 - u43 */
/* si5381: clock-generator@68 {
reg = <0x68>;
};*/
/*
* si5381: clock-generator@68 {
* reg = <0x68>;
* };
*/
};
i2c_si570_user_c0: i2c@2 {
#address-cells = <1>;

16
arch/arm/dts/zynqmp.dtsi
View File

@@ -103,23 +103,23 @@
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
opp00 {
opp-hz = /bits/ 64 <1199999988>;
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
opp01 {
opp-hz = /bits/ 64 <599999994>;
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
opp02 {
opp-hz = /bits/ 64 <399999996>;
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};
opp03 {
opp-hz = /bits/ 64 <299999997>;
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1000000>;
clock-latency-ns = <500000>;
};

32
arch/arm/mach-zynqmp/zynqmp.c
View File

@@ -362,6 +362,35 @@ static int do_zynqmp_reboot(struct cmd_tbl *cmdtp, int flag,
return CMD_RET_SUCCESS;
}
static int do_zynqmp_verify_auth(struct cmd_tbl *cmdtp, int flag,
int argc, char * const argv[])
{
u32 status;
int ret;
ret = zynqmp_mmio_read((ulong)&csu_base->status, &status);
if (ret) {
printf("Can't obtain boot auth state\n");
return CMD_RET_FAILURE;
}
if (status & ZYNQMP_CSU_STATUS_AUTHENTICATED) {
debug("Boot is authenticated\n");
ret = env_set("boot_auth", "1");
if (ret)
return CMD_RET_FAILURE;
} else {
debug("Boot is not authenticated\n");
ret = env_set("boot_auth", "0");
if (ret)
return CMD_RET_FAILURE;
}
return CMD_RET_SUCCESS;
}
static struct cmd_tbl cmd_zynqmp_sub[] = {
U_BOOT_CMD_MKENT(secure, 5, 0, do_zynqmp_verify_secure, "", ""),
U_BOOT_CMD_MKENT(pmufw, 4, 0, do_zynqmp_pmufw, "", ""),
@@ -371,6 +400,7 @@ static struct cmd_tbl cmd_zynqmp_sub[] = {
U_BOOT_CMD_MKENT(rsa, 7, 0, do_zynqmp_rsa, "", ""),
U_BOOT_CMD_MKENT(sha3, 5, 0, do_zynqmp_sha3, "", ""),
U_BOOT_CMD_MKENT(reboot, 3, 0, do_zynqmp_reboot, "", ""),
U_BOOT_CMD_MKENT(verify_auth, 2, 0, do_zynqmp_verify_auth, "", ""),
#ifdef CONFIG_DEFINE_TCM_OCM_MMAP
U_BOOT_CMD_MKENT(tcminit, 3, 0, do_zynqmp_tcm_init, "", ""),
#endif
@@ -446,6 +476,8 @@ U_BOOT_LONGHELP(zynqmp,
" 48 bytes hash value into srcaddr\n"
" Optional key_addr can be specified for saving sha3 hash value\n"
" Note: srcaddr/srclen should not be 0\n"
"zynqmp verify_auth - verifies if boot.bin was authenticated\n"
" Create boot_auth var : 0 not authenticated, 1 authenticated\n"
);
U_BOOT_CMD(

13
arch/microblaze/cpu/spl.c
View File

@@ -14,9 +14,16 @@
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = BOOT_DEVICE_NOR;
spl_boot_list[1] = BOOT_DEVICE_RAM;
spl_boot_list[2] = BOOT_DEVICE_SPI;
u32 i = 0;
if (CONFIG_IS_ENABLED(NOR_SUPPORT))
spl_boot_list[i++] = BOOT_DEVICE_NOR;
if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT))
spl_boot_list[i++] = BOOT_DEVICE_SPI;
if (CONFIG_IS_ENABLED(RAM_SUPPORT))
spl_boot_list[i++] = BOOT_DEVICE_RAM;
}
/* Board initialization after bss clearance */

6
board/amd/versal2/board.c
View File

@@ -253,6 +253,12 @@ static int boot_targets_setup(void)
break;
case EMMC_MODE:
puts("EMMC_MODE\n");
if (uclass_get_device_by_name(UCLASS_MMC,
"mmc@f1050000", &dev)) {
debug("SD1 driver for SD1 device is not present\n");
break;
}
debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
mode = "mmc";
bootseq = dev_seq(dev);
break;

4
board/xilinx/zynqmp/zynqmp.c
View File

@@ -628,6 +628,10 @@ enum env_location env_get_location(enum env_operation op, int prio)
case QSPI_MODE_32BIT:
if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
return ENVL_SPI_FLASH;
if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
return ENVL_FAT;
if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
return ENVL_EXT4;
return ENVL_NOWHERE;
case JTAG_MODE:
default:

4
configs/xilinx_zynqmp_virt_defconfig
View File

@@ -20,6 +20,7 @@ CONFIG_ENV_OFFSET_REDUND=0x1E80000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
CONFIG_CMD_FRU=y
CONFIG_PCI=y
CONFIG_AHCI=y
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
@@ -76,6 +77,7 @@ CONFIG_CMD_MMC=y
CONFIG_MMC_SPEED_MODE_SET=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_PCI=y
CONFIG_CMD_POWEROFF=y
CONFIG_CMD_SDRAM=y
CONFIG_CMD_SF_TEST=y
@@ -180,8 +182,10 @@ CONFIG_PHY_XILINX=y
CONFIG_PHY_XILINX_GMII2RGMII=y
CONFIG_PHY_FIXED=y
CONFIG_DM_ETH_PHY=y
CONFIG_E1000=y
CONFIG_XILINX_AXIEMAC=y
CONFIG_ZYNQ_GEM=y
CONFIG_PCIE_XILINX_NWL=y
CONFIG_POWER_DOMAIN=y
CONFIG_ZYNQMP_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y

17
drivers/pci/pcie-xilinx-nwl.c
View File

@@ -135,6 +135,13 @@ struct nwl_pcie {
u32 ecam_value;
};
static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
{
if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
return true;
return false;
}
static int nwl_pcie_config_address(const struct udevice *bus,
pci_dev_t bdf, uint offset,
void **paddress)
@@ -142,6 +149,9 @@ static int nwl_pcie_config_address(const struct udevice *bus,
struct nwl_pcie *pcie = dev_get_priv(bus);
void *addr;
if (PCI_BUS(bdf) != dev_seq(bus) && !nwl_pcie_link_up(pcie))
return -EIO;
addr = pcie->ecam_base;
addr += PCIE_ECAM_OFFSET(PCI_BUS(bdf) - dev_seq(bus),
PCI_DEV(bdf), PCI_FUNC(bdf), offset);
@@ -181,13 +191,6 @@ static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
writel(val, pcie->breg_base + off);
}
static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
{
if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
return true;
return false;
}
static bool nwl_phy_link_up(struct nwl_pcie *pcie)
{
if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)

178
drivers/phy/phy-zynqmp.c
View File

@@ -82,7 +82,8 @@
/* Reference clock selection parameters */
#define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4)
#define L0_REF_CLK_SEL_MASK 0x8f
#define L0_REF_CLK_LCL_SEL BIT(7)
#define L0_REF_CLK_SEL_MASK 0x9f
/* Calibration digital logic parameters */
#define L3_TM_CALIB_DIG19 0xec4c
@@ -149,24 +150,6 @@
/* Total number of controllers */
#define CONTROLLERS_PER_LANE 5
/* Protocol Type parameters */
enum {
XPSGTR_TYPE_USB0 = 0, /* USB controller 0 */
XPSGTR_TYPE_USB1 = 1, /* USB controller 1 */
XPSGTR_TYPE_SATA_0 = 2, /* SATA controller lane 0 */
XPSGTR_TYPE_SATA_1 = 3, /* SATA controller lane 1 */
XPSGTR_TYPE_PCIE_0 = 4, /* PCIe controller lane 0 */
XPSGTR_TYPE_PCIE_1 = 5, /* PCIe controller lane 1 */
XPSGTR_TYPE_PCIE_2 = 6, /* PCIe controller lane 2 */
XPSGTR_TYPE_PCIE_3 = 7, /* PCIe controller lane 3 */
XPSGTR_TYPE_DP_0 = 8, /* Display Port controller lane 0 */
XPSGTR_TYPE_DP_1 = 9, /* Display Port controller lane 1 */
XPSGTR_TYPE_SGMII0 = 10, /* Ethernet SGMII controller 0 */
XPSGTR_TYPE_SGMII1 = 11, /* Ethernet SGMII controller 1 */
XPSGTR_TYPE_SGMII2 = 12, /* Ethernet SGMII controller 2 */
XPSGTR_TYPE_SGMII3 = 13, /* Ethernet SGMII controller 3 */
};
/* Timeout values */
#define TIMEOUT_US 10000
@@ -195,14 +178,15 @@ struct xpsgtr_ssc {
* struct xpsgtr_phy - representation of a lane
* @dev: pointer to the xpsgtr_dev instance
* @refclk: reference clock index
* @type: controller which uses this lane
* @instance: instance of the protocol type (such as the lane within a
* protocol, or the USB/Ethernet controller)
* @lane: lane number
* @protocol: protocol in which the lane operates
*/
struct xpsgtr_phy {
struct xpsgtr_dev *dev;
unsigned int refclk;
u8 type;
u8 instance;
u8 lane;
u8 protocol;
};
@@ -303,11 +287,12 @@ static void xpsgtr_configure_pll(struct xpsgtr_phy *gtr_phy)
PLL_FREQ_MASK, ssc->pll_ref_clk);
/* Enable lane clock sharing, if required */
if (gtr_phy->refclk != gtr_phy->lane) {
/* Lane3 Ref Clock Selection Register */
if (gtr_phy->refclk == gtr_phy->lane)
xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
L0_REF_CLK_SEL_MASK, L0_REF_CLK_LCL_SEL);
else
xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
L0_REF_CLK_SEL_MASK, 1 << gtr_phy->refclk);
}
/* SSC step size [7:0] */
xpsgtr_clr_set_phy(gtr_phy, L0_PLL_SS_STEP_SIZE_0_LSB,
@@ -459,8 +444,8 @@ static int xpsgtr_init(struct phy *x)
break;
}
dev_dbg(gtr_dev->dev, "lane %u (type %u, protocol %u): init done\n",
gtr_phy->lane, gtr_phy->type, gtr_phy->protocol);
dev_dbg(gtr_dev->dev, "lane %u (protocol %u, instance %u): init done\n",
gtr_phy->lane, gtr_phy->protocol, gtr_phy->instance);
return 0;
}
@@ -469,15 +454,32 @@ static int xpsgtr_init(struct phy *x)
static int xpsgtr_wait_pll_lock(struct phy *phy)
{
struct xpsgtr_dev *gtr_dev = dev_get_priv(phy->dev);
struct xpsgtr_phy *gtr_phy;
u32 phy_lane = phy->id;
int ret = 0;
struct xpsgtr_phy *gtr_phy = &gtr_dev->phys[phy->id];
unsigned int timeout = TIMEOUT_US;
gtr_phy = &gtr_dev->phys[phy_lane];
u8 protocol = gtr_phy->protocol;
int ret = 0;
dev_dbg(gtr_dev->dev, "Waiting for PLL lock\n");
/*
* For DP and PCIe, only the instance 0 PLL is used. Switch to that phy
* so we wait on the right PLL.
*/
if ((protocol == ICM_PROTOCOL_DP || protocol == ICM_PROTOCOL_PCIE) &&
gtr_phy->instance) {
int i;
for (i = 0; i < NUM_LANES; i++) {
gtr_phy = &gtr_dev->phys[i];
if (gtr_phy->protocol == protocol && !gtr_phy->instance)
goto got_phy;
}
return -EBUSY;
}
got_phy:
while (1) {
u32 reg = xpsgtr_read_phy(gtr_phy, L0_PLL_STATUS_READ_1);
@@ -496,104 +498,48 @@ static int xpsgtr_wait_pll_lock(struct phy *phy)
if (ret == -ETIMEDOUT)
dev_err(gtr_dev->dev,
"lane %u (type %u, protocol %u): PLL lock timeout\n",
gtr_phy->lane, gtr_phy->type, gtr_phy->protocol);
"lane %u (protocol %u, instance %u): PLL lock timeout\n",
gtr_phy->lane, gtr_phy->protocol, gtr_phy->protocol);
return ret;
}
static int xpsgtr_power_on(struct phy *phy)
{
struct xpsgtr_dev *gtr_dev = dev_get_priv(phy->dev);
struct xpsgtr_phy *gtr_phy;
u32 phy_lane = phy->id;
int ret = 0;
gtr_phy = &gtr_dev->phys[phy_lane];
/*
* Wait for the PLL to lock. For DP, only wait on DP0 to avoid
* cumulating waits for both lanes. The user is expected to initialize
* lane 0 last.
*/
if (gtr_phy->protocol != ICM_PROTOCOL_DP ||
gtr_phy->type == XPSGTR_TYPE_DP_0)
ret = xpsgtr_wait_pll_lock(phy);
return ret;
return xpsgtr_wait_pll_lock(phy);
}
/*
* OF Xlate Support
*/
/* Set the lane type and protocol based on the PHY type and instance number. */
/* Set the lane protocol and instance based on the PHY type and instance number. */
static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type,
unsigned int phy_instance)
{
unsigned int num_phy_types;
const int *phy_types;
switch (phy_type) {
case PHY_TYPE_SATA: {
static const int types[] = {
XPSGTR_TYPE_SATA_0,
XPSGTR_TYPE_SATA_1,
};
phy_types = types;
num_phy_types = ARRAY_SIZE(types);
case PHY_TYPE_SATA:
num_phy_types = 2;
gtr_phy->protocol = ICM_PROTOCOL_SATA;
break;
}
case PHY_TYPE_USB3: {
static const int types[] = {
XPSGTR_TYPE_USB0,
XPSGTR_TYPE_USB1,
};
phy_types = types;
num_phy_types = ARRAY_SIZE(types);
case PHY_TYPE_USB3:
num_phy_types = 2;
gtr_phy->protocol = ICM_PROTOCOL_USB;
break;
}
case PHY_TYPE_DP: {
static const int types[] = {
XPSGTR_TYPE_DP_0,
XPSGTR_TYPE_DP_1,
};
phy_types = types;
num_phy_types = ARRAY_SIZE(types);
case PHY_TYPE_DP:
num_phy_types = 2;
gtr_phy->protocol = ICM_PROTOCOL_DP;
break;
}
case PHY_TYPE_PCIE: {
static const int types[] = {
XPSGTR_TYPE_PCIE_0,
XPSGTR_TYPE_PCIE_1,
XPSGTR_TYPE_PCIE_2,
XPSGTR_TYPE_PCIE_3,
};
phy_types = types;
num_phy_types = ARRAY_SIZE(types);
case PHY_TYPE_PCIE:
num_phy_types = 4;
gtr_phy->protocol = ICM_PROTOCOL_PCIE;
break;
}
case PHY_TYPE_SGMII: {
static const int types[] = {
XPSGTR_TYPE_SGMII0,
XPSGTR_TYPE_SGMII1,
XPSGTR_TYPE_SGMII2,
XPSGTR_TYPE_SGMII3,
};
phy_types = types;
num_phy_types = ARRAY_SIZE(types);
case PHY_TYPE_SGMII:
num_phy_types = 4;
gtr_phy->protocol = ICM_PROTOCOL_SGMII;
break;
}
default:
return -EINVAL;
}
@@ -601,22 +547,25 @@ static int xpsgtr_set_lane_type(struct xpsgtr_phy *gtr_phy, u8 phy_type,
if (phy_instance >= num_phy_types)
return -EINVAL;
gtr_phy->type = phy_types[phy_instance];
gtr_phy->instance = phy_instance;
return 0;
}
/*
* Valid combinations of controllers and lanes (Interconnect Matrix).
* Valid combinations of controllers and lanes (Interconnect Matrix). Each
* "instance" represents one controller for a lane. For PCIe and DP, the
* "instance" is the logical lane in the link. For SATA, USB, and SGMII,
* the instance is the index of the controller.
*
* This information is only used to validate the devicetree reference, and is
* not used when programming the hardware.
*/
static const unsigned int icm_matrix[NUM_LANES][CONTROLLERS_PER_LANE] = {
{ XPSGTR_TYPE_PCIE_0, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII0 },
{ XPSGTR_TYPE_PCIE_1, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB0,
XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII1 },
{ XPSGTR_TYPE_PCIE_2, XPSGTR_TYPE_SATA_0, XPSGTR_TYPE_USB0,
XPSGTR_TYPE_DP_1, XPSGTR_TYPE_SGMII2 },
{ XPSGTR_TYPE_PCIE_3, XPSGTR_TYPE_SATA_1, XPSGTR_TYPE_USB1,
XPSGTR_TYPE_DP_0, XPSGTR_TYPE_SGMII3 }
/* PCIe, SATA, USB, DP, SGMII */
{ 0, 0, 0, 1, 0 }, /* Lane 0 */
{ 1, 1, 0, 0, 1 }, /* Lane 1 */
{ 2, 0, 0, 1, 2 }, /* Lane 2 */
{ 3, 1, 1, 0, 3 }, /* Lane 3 */
};
/* Translate OF phandle and args to PHY instance. */
@@ -676,7 +625,7 @@ static int xpsgtr_of_xlate(struct phy *x,
* is allowed to operate on the lane.
*/
for (i = 0; i < CONTROLLERS_PER_LANE; i++) {
if (icm_matrix[phy_lane][i] == gtr_phy->type) {
if (icm_matrix[phy_lane][i] == gtr_phy->instance) {
x->id = phy_lane;
return 0;
}
@@ -725,7 +674,10 @@ static int xpsgtr_get_ref_clocks(struct udevice *dev)
}
for (i = 0 ; i < ARRAY_SIZE(ssc_lookup); i++) {
if (rate == ssc_lookup[i].refclk_rate) {
/* Allow an error of 100 ppm */
unsigned long error = ssc_lookup[i].refclk_rate / 10000;
if (abs(rate - ssc_lookup[i].refclk_rate) < error) {
gtr_dev->refclk_sscs[refclk] = &ssc_lookup[i];
dev_dbg(dev, "Found rate %d\n", i);
break;

8
drivers/ufs/ufs-amd-versal2.c
View File

@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2024 Advanced Micro Devices, Inc.
* Copyright (C) 2024-2025 Advanced Micro Devices, Inc.
*/
#include <clk.h>
@@ -305,7 +305,7 @@ static int ufs_versal2_init(struct ufs_hba *hba)
priv->phy_mode = UFSHCD_DWC_PHY_MODE_ROM;
ret = clk_get_by_name(hba->dev, "core_clk", &clk);
ret = clk_get_by_name(hba->dev, "core", &clk);
if (ret) {
dev_err(hba->dev, "failed to get core_clk clock\n");
return ret;
@@ -319,12 +319,12 @@ static int ufs_versal2_init(struct ufs_hba *hba)
}
priv->host_clk = core_clk_rate;
priv->rstc = devm_reset_control_get(hba->dev, "ufshc-rst");
priv->rstc = devm_reset_control_get(hba->dev, "host");
if (IS_ERR(priv->rstc)) {
dev_err(hba->dev, "failed to get reset ctl: ufshc-rst\n");
return PTR_ERR(priv->rstc);
}
priv->rstphy = devm_reset_control_get(hba->dev, "ufsphy-rst");
priv->rstphy = devm_reset_control_get(hba->dev, "phy");
if (IS_ERR(priv->rstphy)) {
dev_err(hba->dev, "failed to get reset ctl: ufsphy-rst\n");
return PTR_ERR(priv->rstphy);

8
include/configs/amd_versal2.h
View File

@@ -49,12 +49,12 @@
#define ENV_MEM_LAYOUT_SETTINGS \
"fdt_addr_r=0x40000000\0" \
"fdt_size_r=0x400000\0" \
"pxefile_addr_r=0x10000000\0" \
"kernel_addr_r=0x18000000\0" \
"pxefile_addr_r=0x70000000\0" \
"kernel_addr_r=0x48000000\0" \
"kernel_size_r=0x10000000\0" \
"kernel_comp_addr_r=0x30000000\0" \
"kernel_comp_addr_r=0x50000000\0" \
"kernel_comp_size=0x3C00000\0" \
"ramdisk_addr_r=0x02100000\0" \
"ramdisk_addr_r=0x60000000\0" \
"script_size_f=0x80000\0"
#if defined(CONFIG_DISTRO_DEFAULTS)