Merge tag 'v2026.01-rc4' into next

Prepare v2026.01-rc4
2025-12-08 13:17:27 -06:00
parent 8e12d6ccb3 0e0a198a68
commit 59202e5ae7
201 changed files with 7926 additions and 376 deletions
--- a/.mailmap
+++ b/.mailmap
@@ -28,6 +28,7 @@ Anurag Kumar Vulisha <AnuragKumar.Vulisha@amd.com> <anurag.kumar.vulisha@xilinx.
 Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com> <appana.durga.rao@xilinx.com>
 Ashok Reddy Soma <ashok.reddy.soma@amd.com> <ashok.reddy.soma@xilinx.com>
 Atish Patra <atishp@atishpatra.org> <atish.patra@wdc.com>
+Bernhard Messerklinger <bernhard.messerklinger@at.abb.com> <bernhard.messerklinger@br-automation.com>
 Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharat.kumar.gogada@xilinx.com>
 Bharat Kumar Gogada <bharat.kumar.gogada@amd.com> <bharatku@xilinx.com>
 Bhargava Sreekantappa Gayathri <bhargava.sreekantappa-gayathri@amd.com> <bhargava.sreekantappa-gayathri@xilinx.com>
@@ -74,6 +75,7 @@ Jyotheeswar Reddy Mutthareddyvari <jyotheeswar.reddy.mutthareddyvari@amd.com> <j
 Kalyani Akula <kalyani.akula@amd.com> <kalyani.akula@xilinx.com>
 Klaus Goger <klaus.goger@cherry.de> <klaus.goger@theobroma-systems.com>
 Masahisa Kojima <kojima.masahisa@socionext.com> <masahisa.kojima@linaro.org>
+Linus Walleij <linusw@kernel.org> <linus.walleij@linaro.org>
 Love Kumar <love.kumar@amd.com> <love.kumar@xilinx.com>
 Lukasz Majewski <lukma@denx.de>
 Marek Behún <kabel@kernel.org> <marek.behun@nic.cz>
@@ -156,6 +158,8 @@ Wolfgang Denk <wd@denx.de> <wd@pollux.(none)>
 Wolfgang Denk <wd@denx.de> <wd@pollux.denx.de>
 Wolfgang Denk <wd@denx.de> <wd@xpert.denx.de>
 Wolfgang Denk <wd@denx.de> <wdenk>
+Wolfgang Wallner <wolfgang.wallner@at.abb.com> <wolfgang.wallner@br-automation.com>
+Yao Zi <me@ziyao.cc> <ziyao@disroot.org>
 York Sun <york.sun@nxp.com>
 York Sun <yorksun@freescale.com>
 Łukasz Majewski <l.majewski@samsung.com>
--- a/7
+++ b/7
@@ -820,7 +820,7 @@ F:	include/linux/soc/ti/

 ARM U8500
 M:	Stephan Gerhold <stephan@gerhold.net>
-R:	Linus Walleij <linus.walleij@linaro.org>
+R:	Linus Walleij <linusw@kernel.org>
 S:	Maintained
 F:	arch/arm/dts/ste-*
 F:	arch/arm/mach-u8500/
@@ -1039,7 +1039,6 @@ F:	drivers/mtd/jedec_flash.c

 CLOCK
 M:	Lukasz Majewski <lukma@denx.de>
-M:	Sean Anderson <seanga2@gmail.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-clk.git
 F:	drivers/clk/
@@ -1617,7 +1616,7 @@ F:	drivers/pinctrl/pinctrl-k210.c
 F:	include/k210/

 RISC-V T-HEAD TH1520
-M:	Yao Zi <ziyao@disroot.org>
+M:	Yao Zi <me@ziyao.cc>
 S:	Maintained
 F:	arch/riscv/cpu/th1520/
 F:	drivers/clk/thead/clk-th1520-ap.c
@@ -1660,7 +1659,7 @@ F:	include/scmi*
 N:	scmi

 SEAMA
-M:	Linus Walleij <linus.walleij@linaro.org>
+M:	Linus Walleij <linusw@kernel.org>
 S:	Maintained
 F:	cmd/seama.c
 F:	doc/usage/cmd/seama.rst
--- a/11
+++ b/11
@@ -3,7 +3,7 @@
 VERSION = 2026
 PATCHLEVEL = 01
 SUBLEVEL =
-EXTRAVERSION = -rc3
+EXTRAVERSION = -rc4
 NAME =

 # *DOCUMENTATION*
@@ -1499,6 +1499,15 @@ ifeq ($(CONFIG_POSITION_INDEPENDENT)$(CONFIG_RCAR_GEN3),yy)
 OBJCOPYFLAGS_u-boot-elf.srec += --change-addresses=0x50000000
 endif

+ifeq ($(CONFIG_POSITION_INDEPENDENT)$(CONFIG_RCAR_GEN5),yy)
+# The flash_writer tool and previous recovery tools
+# require the SREC load address to be 0x8e30_0000 .
+# The PIE U-Boot build sets the address to 0x0, so
+# override the address back to make u-boot-elf.srec
+# compatible with the recovery tools.
+OBJCOPYFLAGS_u-boot-elf.srec += --change-addresses=0x8e300000
+endif
+
 u-boot-elf.srec: u-boot.elf FORCE
 	$(call if_changed,zobjcopy)

--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -58,7 +58,7 @@ endif

 # Only test once
 ifeq ($(CONFIG_$(PHASE_)SYS_THUMB_BUILD),y)
-archprepare: checkthumb checkgcc6
+archprepare: checkthumb checkgcc10

 checkthumb:
 	@if test "$(call cc-name)" = "gcc" -a \
@@ -69,13 +69,13 @@ checkthumb:
 		false; \
 	fi
 else
-archprepare: checkgcc6
+archprepare: checkgcc10
 endif

-checkgcc6:
+checkgcc10:
 	@if test "$(call cc-name)" = "gcc" -a \
-			"$(call cc-version)" -lt "0600"; then \
-		echo '*** Your GCC is older than 6.0 and is not supported'; \
+			"$(call cc-version)" -lt "1000"; then \
+		echo '*** Your GCC is older than 10.0 and is not supported'; \
 		false; \
 	fi

--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -918,6 +918,13 @@ dtb-$(CONFIG_RZA1) += \
 	r7s72100-genmai.dtb \
 	r7s72100-gr-peach.dtb

+dtb-$(CONFIG_RCAR_GEN5) += \
+	r8a78000-ironhide.dtb
+
+ifdef CONFIG_RCAR_GEN5
+DTC_FLAGS += -R 4 -p 0x1000
+endif
+
 dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb

 dtb-$(CONFIG_TARGET_PM9261) += at91sam9261ek.dtb
--- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
@@ -10,16 +10,16 @@
 		compatible = "fsl,imx8ulp-mu";
 		reg = <0 0x27020000 0 0x10000>;
 		status = "okay";
-		bootph-pre-ram;
+		bootph-all;
 	};
 };

 &soc {
-	bootph-pre-ram;
+	bootph-all;
 };

 &per_bridge3 {
-	bootph-pre-ram;
+	bootph-all;
 };

 &per_bridge4 {
@@ -27,15 +27,15 @@
 };

 &iomuxc1 {
-	bootph-pre-ram;
+	bootph-all;
 };

 &pinctrl_lpuart5 {
-	bootph-pre-ram;
+	bootph-all;
 };

 &lpuart5 {
-	bootph-pre-ram;
+	bootph-all;
 };

 &usdhc0 {
--- a/arch/arm/dts/imx8ulp-evk.dts
+++ b/arch/arm/dts/imx8ulp-evk.dts
@@ -119,3 +119,7 @@
 		>;
 	};
 };
+
+&wdog3 {
+	status = "disabled";
+};
--- a/arch/arm/dts/imx91-11x11-evk.dts
+++ b/arch/arm/dts/imx91-11x11-evk.dts
@@ -503,7 +503,7 @@
 			MX91_PAD_ENET1_TD0__GPIO4_IO5                          0x31e
 			MX91_PAD_ENET1_TD1__GPIO4_IO4                          0x31e
 			MX91_PAD_ENET1_TD2__GPIO4_IO3				0x31e
-			MX91_PAD_ENET1_TD3__GPIO4_IO3				0x31e
+			MX91_PAD_ENET1_TD3__GPIO4_IO2				0x31e
 			MX91_PAD_ENET1_TXC__GPIO4_IO7                          0x31e
 			MX91_PAD_ENET1_TX_CTL__GPIO4_IO6                       0x31e
 		>;
--- a/arch/arm/dts/imx91-pinfunc.h
+++ b/arch/arm/dts/imx91-pinfunc.h
@@ -330,7 +330,7 @@
 #define MX91_PAD_ENET1_TD3__CAN2_TX                                              0x00a0 0x0250 0x0000 0x02 0x00
 #define MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2                                      0x00a0 0x0250 0x0000 0x03 0x00
 #define MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2                                      0x00a0 0x0250 0x0000 0x04 0x00
-#define MX91_PAD_ENET1_TD3__GPIO4_IO3                                            0x00a0 0x0250 0x0000 0x05 0x00
+#define MX91_PAD_ENET1_TD3__GPIO4_IO2                                            0x00a0 0x0250 0x0000 0x05 0x00
 #define MX91_PAD_ENET1_TD3__LPI2C2_SCL                                           0x00a0 0x0250 0x03e8 0x06 0x00

 #define MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2                                   0x00a4 0x0254 0x0000 0x00 0x00
@@ -680,7 +680,7 @@
 #define MX91_PAD_I2C2_SCL__LPUART2_DCB_B                                         0x0178 0x0328 0x0000 0x02 0x00
 #define MX91_PAD_I2C2_SCL__TPM2_CH2                                              0x0178 0x0328 0x0000 0x03 0x00
 #define MX91_PAD_I2C2_SCL__SAI1_RX_SYNC                                          0x0178 0x0328 0x0000 0x04 0x00
-#define MX91_PAD_I2C2_SCL__GPIO1_IO3                                             0x0178 0x0328 0x0000 0x05 0x00
+#define MX91_PAD_I2C2_SCL__GPIO1_IO2                                             0x0178 0x0328 0x0000 0x05 0x00
 #define MX91_PAD_I2C2_SCL__I3C1_PUR_B                                            0x0178 0x0328 0x0000 0x06 0x00

 #define MX91_PAD_I2C2_SDA__LPI2C2_SDA                                            0x017c 0x032c 0x03ec 0x00 0x01
--- a/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
+++ b/arch/arm/dts/r8a779g0-white-hawk-u-boot.dtsi
@@ -23,8 +23,6 @@

 &rpc {
 	bootph-all;
-	status = "disabled";
-
 	flash@0 {
 		bootph-all;
 		spi-tx-bus-width = <1>;
--- a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi
+++ b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source extras for U-Boot for the Ironhide board
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include "r8a78000-u-boot.dtsi"
--- a/arch/arm/dts/r8a78000-ironhide.dts
+++ b/arch/arm/dts/r8a78000-ironhide.dts
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source for the Ironhide board
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a78000.dtsi"
+#include <dt-bindings/net/ti-dp83869.h>
+
+/ {
+	model = "Renesas Ironhide board based on r8a78000";
+	compatible = "renesas,ironhide", "renesas,r8a78000";
+
+	aliases {
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		i2c7 = &i2c7;
+		i2c8 = &i2c8;
+		mmc0 = &mmc0;
+		serial0 = &hscif0;
+	};
+
+	chosen {
+		stdout-path = "serial0:1843200n8";
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x0 0x80000000>;
+	};
+
+	memory@1080000000 {
+		device_type = "memory";
+		reg = <0x10 0x80000000 0x0 0x80000000>;
+	};
+
+	memory@1200000000 {
+		device_type = "memory";
+		reg = <0x12 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1400000000 {
+		device_type = "memory";
+		reg = <0x14 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1600000000 {
+		device_type = "memory";
+		reg = <0x16 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1800000000 {
+		device_type = "memory";
+		reg = <0x18 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1a00000000 {
+		device_type = "memory";
+		reg = <0x1a 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1c00000000 {
+		device_type = "memory";
+		reg = <0x1c 0x00000000 0x1 0x00000000>;
+	};
+
+	memory@1e00000000 {
+		device_type = "memory";
+		reg = <0x1e 0x00000000 0x1 0x00000000>;
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&extal_clk {
+	clock-frequency = <16666600>;
+};
+
+&extalr_clk {
+	clock-frequency = <32768>;
+};
+
+&hscif0 {
+	pinctrl-0 = <&hscif0_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-0 = <&i2c0_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <400000>;
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "rohm,br24g01", "atmel,24c01";
+		reg = <0x50>;
+		pagesize = <8>;
+	};
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_pins>;
+	pinctrl-names = "default";
+	clock-frequency = <400000>;
+	status = "okay";
+};
+
+&eth_pcs {
+	phys = <&mp_phy 2 1>;
+	status = "okay";
+};
+
+&mmc0 {
+	pinctrl-0 = <&mmc0_pins>;
+	pinctrl-1 = <&mmc0_pins>;
+	pinctrl-names = "default", "state_uhs";
+
+	bus-width = <8>;
+	full-pwr-cycle-in-suspend;
+	mmc-hs200-1_8v;
+	mmc-hs400-1_8v;
+	no-sd;
+	no-sdio;
+	non-removable;
+
+	vmmc-supply = <&reg_3p3v>;
+	vqmmc-supply = <&reg_1p8v>;
+
+	status = "okay";
+};
+
+&ufs0 {
+	status = "okay";
+};
+
+&ufs1 {
+	status = "okay";
+};
+
+&mp_phy {
+	status = "okay";
+};
+
+&pfc {
+	pinctrl-0 = <&scif_clk_pins>;
+	pinctrl-names = "default";
+
+	eth25g2_pins: eth25g2 {
+		groups = "eth25g2_mdio", "eth25g2_link", "eth25g2_phyint";
+		function = "eth25g2";
+		drive-strength = <24>;
+	};
+
+	ethes0_pins: ethes0 {
+		groups = "ethes0_match", "ethes0_capture", "ethes0_pps";
+		function = "ethes0";
+		drive-strength = <24>;
+	};
+
+	hscif0_pins: hscif0 {
+		groups = "hscif0_data", "hscif0_ctrl";
+		function = "hscif0";
+	};
+
+	i2c0_pins: i2c0 {
+		groups = "i2c0";
+		function = "i2c0";
+	};
+
+	i2c1_pins: i2c1 {
+		groups = "i2c1";
+		function = "i2c1";
+	};
+
+	mmc0_pins: mmc0 {
+		groups = "mmc0_data8", "mmc0_ctrl", "mmc0_ds";
+		function = "mmc0";
+		drive-strength = <24>;
+	};
+
+	rsw3_pins: rsw3 {
+		groups = "rsw3_match", "rsw3_capture", "rsw3_pps";
+		function = "rsw3";
+		drive-strength = <24>;
+	};
+
+	scif_clk_pins: scif-clk {
+		groups = "scif_clk";
+		function = "scif_clk";
+	};
+};
+
+&rswitch3 {
+	pinctrl-0 = <&rsw3_pins>, <&eth25g2_pins>, <&ethes0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	ethernet-ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/*
+		 * NOTE: Only port@4 is configured for R-Car X5H board.
+		 * Other ports (0-3, 5-12) are currently unused or not
+		 * connected.
+		 */
+		port@4 {
+			reg = <4>;
+			renesas,connect_to_xpcs;
+			phy-handle = <&dp83869_phy>;
+			phy-mode = "sgmii";
+			phys = <&eth_pcs 5>;
+
+			mdio {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				dp83869_phy: ethernet-phy@2 {
+					reg = <2>;
+					ti,sgmii-interface;
+					ti,max-output-impedance;
+					ti,refclk-output-enable;
+					ti,clk-output-sel = <DP83869_CLK_O_SEL_REF_CLK>;
+				};
+			};
+		};
+	};
+};
+
+&scif_clk {
+	clock-frequency = <26000000>;
+};
--- a/arch/arm/dts/r8a78000-u-boot.dtsi
+++ b/arch/arm/dts/r8a78000-u-boot.dtsi
@@ -0,0 +1,139 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Source extras for U-Boot on R-Car R8A78000 SoC
+ *
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+/ {
+	soc {
+		bootph-all;
+	};
+
+	/* Placeholder clock until the clock provider is in place */
+	clk_stub_gpio: clk-stub-gpio {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000>;
+	};
+
+	clk_stub_i2c0: clk-stub-i2c0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <150000000>;
+	};
+
+	clk_stub_i2c1: clk-stub-i2c1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <133333333>;
+	};
+
+	clk_stub_mmc: clk-stub-mmc {
+		compatible = "renesas,compound-clock";
+		#clock-cells = <0>;
+		clocks = <&scmi_clk SCP_CLOCK_ID_MDLC_SDHI0>,
+			 <&scmi_clk 1691>;
+		clock-names = "mdlc", "per";
+	};
+};
+
+&cpg {
+	bootph-all;
+};
+
+&extal_clk {
+	bootph-all;
+};
+
+&extalr_clk {
+	bootph-all;
+};
+
+&gpio0 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio1 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio2 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio3 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio4 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio5 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio6 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio7 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio8 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio9 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&gpio10 {
+	clocks = <&clk_stub_gpio>;
+};
+
+&i2c0 {
+	clocks = <&clk_stub_i2c0>;
+};
+
+&i2c1 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&i2c2 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&i2c3 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&i2c4 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&i2c5 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&i2c6 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&i2c7 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&i2c8 {
+	clocks = <&clk_stub_i2c1>;
+};
+
+&mmc0 {
+	clocks = <&clk_stub_mmc>;
+};
+
+&prr {
+	bootph-all;
+};
--- a/arch/arm/dts/r8a78000.dtsi
+++ b/arch/arm/dts/r8a78000.dtsi
--- a/arch/arm/dts/socfpga-common-u-boot.dtsi
+++ b/arch/arm/dts/socfpga-common-u-boot.dtsi
@@ -5,6 +5,10 @@
 * Copyright (c) 2019 Simon Goldschmidt
 */
 /{
+	memory {
+		bootph-all;
+	};
+
 	soc {
 		bootph-all;
 	};
@@ -14,6 +18,10 @@
 	bootph-all;
 };

+&L2 {
+	bootph-all;
+};
+
 &rst {
 	bootph-all;
 };
--- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
@@ -13,6 +13,32 @@
 		spi0 = "/soc/spi@ff705000";
 		udc0 = &usb1;
 	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			default-state = "off";
+			gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+		};
+
+		led-1 {
+			default-state = "off";
+			gpios = <&portb 25 GPIO_ACTIVE_HIGH>;
+			label = "status_1";
+		};
+
+		led-2 {
+			default-state = "off";
+			gpios = <&portb 26 GPIO_ACTIVE_HIGH>;
+			label = "status_2";
+		};
+
+		led-3 {
+			default-state = "off";
+			gpios = <&portc 7 GPIO_ACTIVE_HIGH>;
+		};
+	};
 };

 &mmc {
--- a/arch/arm/include/asm/arch-imx9/imx91_pins.h
+++ b/arch/arm/include/asm/arch-imx9/imx91_pins.h
@@ -329,7 +329,7 @@ enum {
 	MX91_PAD_ENET1_TD3__CAN2_TX                                                     = IOMUX_PAD(0x0250, 0x00A0, 0x02, 0x0000, 0x00, 0x00),
 	MX91_PAD_ENET1_TD3__HSIOMIX_OTG_ID2                                             = IOMUX_PAD(0x0250, 0x00A0, 0x03, 0x0000, 0x00, 0x00),
 	MX91_PAD_ENET1_TD3__FLEXIO2_FLEXIO2                                             = IOMUX_PAD(0x0250, 0x00A0, 0x04, 0x0000, 0x00, 0x00),
-	MX91_PAD_ENET1_TD3__GPIO4_IO3                                                   = IOMUX_PAD(0x0250, 0x00A0, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_ENET1_TD3__GPIO4_IO2                                                   = IOMUX_PAD(0x0250, 0x00A0, 0x05, 0x0000, 0x00, 0x00),
 	MX91_PAD_ENET1_TD3__LPI2C2_SCL                                                  = IOMUX_PAD(0x0250, 0x00A0, 0x06, 0x03E8, 0x00, 0x00),

 	MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2                                          = IOMUX_PAD(0x0254, 0x00A4, 0x00, 0x0000, 0x00, 0x00),
@@ -679,7 +679,7 @@ enum {
 	MX91_PAD_I2C2_SCL__LPUART2_DCB_B                                                = IOMUX_PAD(0x0328, 0x0178, 0x02, 0x0000, 0x00, 0x00),
 	MX91_PAD_I2C2_SCL__TPM2_CH2                                                     = IOMUX_PAD(0x0328, 0x0178, 0x03, 0x0000, 0x00, 0x00),
 	MX91_PAD_I2C2_SCL__SAI1_RX_SYNC                                                 = IOMUX_PAD(0x0328, 0x0178, 0x04, 0x0000, 0x00, 0x00),
-	MX91_PAD_I2C2_SCL__GPIO1_IO3                                                    = IOMUX_PAD(0x0328, 0x0178, 0x05, 0x0000, 0x00, 0x00),
+	MX91_PAD_I2C2_SCL__GPIO1_IO2                                                    = IOMUX_PAD(0x0328, 0x0178, 0x05, 0x0000, 0x00, 0x00),
 	MX91_PAD_I2C2_SCL__I3C1_PUR_B                                                   = IOMUX_PAD(0x0328, 0x0178, 0x06, 0x0000, 0x00, 0x00),

 	MX91_PAD_I2C2_SDA__LPI2C2_SDA                                                   = IOMUX_PAD(0x032C, 0x017C, 0x00, 0x03EC, 0x01, 0x00),
--- a/arch/arm/mach-bcm283x/include/mach/gpio.h
+++ b/arch/arm/mach-bcm283x/include/mach/gpio.h
@@ -26,6 +26,16 @@
 #define BCM2835_GPIO_FSEL_BANK(gpio)	(gpio / 10)
 #define BCM2835_GPIO_FSEL_SHIFT(gpio)	((gpio % 10) * 3)

+/* BCM2835 GPIO Pull-up/down register offsets */
+#define BCM2835_GPPUD		37
+#define BCM2835_GPPUDCLK0	38
+
+/* BCM2711 GPIO Pull-up/down control */
+#define BCM2711_GPPUD_CNTRL_REG0	57
+#define BCM2711_PUD_REG_OFFSET(gpio)	((gpio) / 16)
+#define BCM2711_PUD_REG_SHIFT(gpio)	(((gpio) % 16) * 2)
+#define BCM2711_PUD_2711_MASK		0x3
+
 struct bcm2835_gpio_regs {
 	u32 gpfsel[6];
 	u32 reserved1;
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -2,7 +2,7 @@ if ARCH_EXYNOS

 config BOARD_COMMON
 	def_bool y
-	depends on !TARGET_SMDKV310 && !TARGET_ARNDALE && !TARGET_E850_96
+	depends on !TARGET_SMDKV310 && !TARGET_ARNDALE && !TARGET_EXYNOS_MOBILE && !TARGET_E850_96

 config SPI_BOOTING
 	bool
@@ -252,6 +252,14 @@ config TARGET_E850_96
 endchoice
 endif

+config TARGET_EXYNOS_MOBILE
+	bool "Samsung Exynos Generic Boards (for mobile devices)"
+	select ARM64
+	select BOARD_EARLY_INIT_F
+	select CLK_EXYNOS
+	select LINUX_KERNEL_IMAGE_HEADER
+	select OF_CONTROL
+
 config SYS_SOC
 	default "exynos"

@@ -277,5 +285,6 @@ source "board/samsung/smdk5420/Kconfig"
 source "board/samsung/espresso7420/Kconfig"
 source "board/samsung/axy17lte/Kconfig"
 source "board/samsung/e850-96/Kconfig"
+source "board/samsung/exynos-mobile/Kconfig"

 endif
--- a/arch/arm/mach-k3/r5/j722s/clk-data.c
+++ b/arch/arm/mach-k3/r5/j722s/clk-data.c
@@ -68,6 +68,11 @@ static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
 	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
 };

+static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
+	"postdiv4_16ff_main_0_hsdivout5_clk",
+	"hsdiv4_16fft_main_2_hsdivout2_clk",
+};
+
 static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
 	"postdiv4_16ff_main_0_hsdivout5_clk",
 	"hsdiv4_16fft_main_2_hsdivout2_clk",
@@ -106,6 +111,8 @@ static const char * const main_timerclkn_sel_out0_parents[] = {
 	NULL,
 	NULL,
 	NULL,
+	NULL,
+	NULL,
 };

 static const char * const wkup_clkout_sel_out0_parents[] = {
@@ -205,6 +212,7 @@ static const struct clk_data clk_list[] = {
 	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
 	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
 	CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
+	CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
 	CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
 	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
 	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
@@ -262,6 +270,10 @@ static const struct dev_clk soc_dev_clk_data[] = {
 	DEV_CLK(36, 10, "board_0_cp_gemac_cpts0_rft_clk_out"),
 	DEV_CLK(36, 11, "hsdiv4_16fft_main_1_hsdivout3_clk"),
 	DEV_CLK(36, 12, "postdiv4_16ff_main_2_hsdivout6_clk"),
+	DEV_CLK(57, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+	DEV_CLK(57, 2, "main_emmcsd0_refclk_sel_out0"),
+	DEV_CLK(57, 3, "postdiv4_16ff_main_0_hsdivout5_clk"),
+	DEV_CLK(57, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
 	DEV_CLK(36, 13, "cpsw_3guss_am67_main_0_cpts_genf0"),
 	DEV_CLK(36, 14, "cpsw_3guss_am67_main_0_cpts_genf1"),
 	DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
--- a/arch/arm/mach-k3/r5/j722s/dev-data.c
+++ b/arch/arm/mach-k3/r5/j722s/dev-data.c
@@ -23,18 +23,19 @@ static struct ti_pd soc_pd_list[] = {

 static struct ti_lpsc soc_lpsc_list[] = {
 	[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
-	[1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
-	[2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[4]),
-	[3] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
-	[4] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
-	[5] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
-	[6] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
-	[7] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[6]),
-	[8] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[6]),
-	[9] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
-	[10] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[6]),
-	[11] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[10]),
-	[12] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
+	[1] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
+	[2] = PSC_LPSC(13, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[5]),
+	[3] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
+	[4] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
+	[5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
+	[6] = PSC_LPSC(28, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
+	[7] = PSC_LPSC(34, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
+	[8] = PSC_LPSC(42, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[7]),
+	[9] = PSC_LPSC(53, &soc_psc_list[0], &soc_pd_list[1], &soc_lpsc_list[7]),
+	[10] = PSC_LPSC(56, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[9]),
+	[11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]),
+	[12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
+	[13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
 };

 static struct ti_dev soc_dev_list[] = {
@@ -43,18 +44,19 @@ static struct ti_dev soc_dev_list[] = {
 	PSC_DEV(61, &soc_lpsc_list[0]),
 	PSC_DEV(178, &soc_lpsc_list[1]),
 	PSC_DEV(179, &soc_lpsc_list[2]),
-	PSC_DEV(58, &soc_lpsc_list[3]),
-	PSC_DEV(161, &soc_lpsc_list[4]),
-	PSC_DEV(75, &soc_lpsc_list[5]),
-	PSC_DEV(36, &soc_lpsc_list[6]),
-	PSC_DEV(102, &soc_lpsc_list[6]),
-	PSC_DEV(146, &soc_lpsc_list[6]),
-	PSC_DEV(13, &soc_lpsc_list[7]),
-	PSC_DEV(166, &soc_lpsc_list[8]),
-	PSC_DEV(135, &soc_lpsc_list[9]),
-	PSC_DEV(170, &soc_lpsc_list[10]),
-	PSC_DEV(177, &soc_lpsc_list[11]),
-	PSC_DEV(55, &soc_lpsc_list[12]),
+	PSC_DEV(57, &soc_lpsc_list[3]),
+	PSC_DEV(58, &soc_lpsc_list[4]),
+	PSC_DEV(161, &soc_lpsc_list[5]),
+	PSC_DEV(75, &soc_lpsc_list[6]),
+	PSC_DEV(36, &soc_lpsc_list[7]),
+	PSC_DEV(102, &soc_lpsc_list[7]),
+	PSC_DEV(146, &soc_lpsc_list[7]),
+	PSC_DEV(13, &soc_lpsc_list[8]),
+	PSC_DEV(166, &soc_lpsc_list[9]),
+	PSC_DEV(135, &soc_lpsc_list[10]),
+	PSC_DEV(170, &soc_lpsc_list[11]),
+	PSC_DEV(177, &soc_lpsc_list[12]),
+	PSC_DEV(55, &soc_lpsc_list[13]),
 };

 const struct ti_k3_pd_platdata j722s_pd_platdata = {
--- a/arch/arm/mach-renesas/Kconfig
+++ b/arch/arm/mach-renesas/Kconfig
@@ -46,6 +46,11 @@ config RCAR_GEN4
 	select RCAR_64
 	select PINCTRL_PFC

+config RCAR_GEN5
+	bool "Renesas ARM SoCs R-Car Gen5 (64bit)"
+	select RCAR_64
+	select PINCTRL_PFC
+
 config RZA1
 	prompt "Renesas ARM SoCs RZ/A1 (32bit)"
 	select CPU_V7A
--- a/arch/arm/mach-renesas/Kconfig.64
+++ b/arch/arm/mach-renesas/Kconfig.64
@@ -8,5 +8,6 @@ config OF_LIBFDT_OVERLAY

 source "arch/arm/mach-renesas/Kconfig.rcar3"
 source "arch/arm/mach-renesas/Kconfig.rcar4"
+source "arch/arm/mach-renesas/Kconfig.rcar5"

 endif
--- a/arch/arm/mach-renesas/Kconfig.rcar5
+++ b/arch/arm/mach-renesas/Kconfig.rcar5
@@ -0,0 +1,26 @@
+if RCAR_GEN5
+
+menu "Select Target SoC"
+
+config R8A78000
+	bool "Renesas SoC R8A78000"
+	select GICV3
+	imply PINCTRL_PFC_R8A78000
+
+endmenu
+
+choice
+	prompt "Renesas ARM64 SoCs board select"
+	optional
+
+config TARGET_IRONHIDE
+	bool "Ironhide board"
+	imply R8A78000
+	help
+	  Support for Renesas R-Car Gen5 Ironhide platform
+
+endchoice
+
+source "board/renesas/ironhide/Kconfig"
+
+endif
--- a/arch/arm/mach-renesas/Makefile
+++ b/arch/arm/mach-renesas/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o
 obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o
 obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o memmap-gen3.o
 obj-$(CONFIG_RCAR_GEN4) += cpu_info-rcar.o memmap-gen3.o
+obj-$(CONFIG_RCAR_GEN5) += cpu_info-rcar.o memmap-gen3.o
 obj-$(CONFIG_RZ_G2) += cpu_info-rzg.o
 obj-$(CONFIG_RZG2L) += cpu_info-rzg2l.o memmap-rzg2l.o

--- a/arch/arm/mach-renesas/cpu_info-rcar.c
+++ b/arch/arm/mach-renesas/cpu_info-rcar.c
@@ -15,8 +15,12 @@

 static u32 renesas_get_prr(void)
 {
-	if (IS_ENABLED(CONFIG_RCAR_64))
-		return readl(0xFFF00044);
+	if (IS_ENABLED(CONFIG_RCAR_64)) {
+		if (IS_ENABLED(CONFIG_RCAR_GEN5))
+			return readl(0x189E0044);
+		else
+			return readl(0xFFF00044);
+	}

 	return readl(0xFF000044);
 }
--- a/arch/arm/mach-renesas/cpu_info.c
+++ b/arch/arm/mach-renesas/cpu_info.c
@@ -72,6 +72,7 @@ static const struct {
 	{ RENESAS_CPU_TYPE_R8A779F0, "R8A779F0" },
 	{ RENESAS_CPU_TYPE_R8A779G0, "R8A779G0" },
 	{ RENESAS_CPU_TYPE_R8A779H0, "R8A779H0" },
+	{ RMOBILE_CPU_TYPE_R8A78000, "R8A78000" },
 	{ 0x0, "CPU" },
 };

--- a/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h
+++ b/arch/arm/mach-renesas/include/mach/rcar-gen5-base.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#ifndef __ASM_ARCH_RCAR_GEN5_BASE_H
+#define __ASM_ARCH_RCAR_GEN5_BASE_H
+
+/*
+ * R-Car (R8A78000) I/O Addresses
+ */
+#define TMU_BASE		0x1C030000
+
+/* Arm Generic Timer */
+#define CNTCR_BASE		0x1C000FFF /* Region 0 */
+#define CNTFID0			(CNTCR_BASE + 0x020)
+#define CNTCR_EN		BIT(0)
+
+/* Reset */
+#define RST_BASE		0xC1320000 /* Domain0 */
+#define RST_SWSRES1A		(RST_BASE + 0x410)
+#define RST_WDTRSTCR		(RST_BASE + 0x420)
+#define RST_RWDT_RSTMSK		BIT(0)
+#define RST_WWDT_RSTMSK		BIT(2)
+#define RST_RESKCPROT0		(RST_BASE + 0x4F0)
+#define RST_KCPROT_DIS		0xA5A5A501
+
+/* GICv4 */
+/* Distributor Registers */
+#define GICD_BASE		0x38000000
+#define GICR_BASE		(GICR_LPI_BASE)
+
+/* ReDistributor Registers for Control and Physical LPIs */
+#define GICR_LPI_BASE		0x38080000
+#define GICR_WAKER		0x0014
+#define GICR_PWRR		0x0024
+#define GICR_LPI_WAKER		(GICR_LPI_BASE + GICR_WAKER)
+#define GICR_LPI_PWRR		(GICR_LPI_BASE + GICR_PWRR)
+
+/* ReDistributor Registers for SGIs and PPIs */
+#define GICR_SGI_BASE		0x38090000
+#define GICR_IGROUPR0		0x0080
+
+#endif /* __ASM_ARCH_RCAR_GEN5_BASE_H */
--- a/arch/arm/mach-renesas/include/mach/renesas.h
+++ b/arch/arm/mach-renesas/include/mach/renesas.h
@@ -16,6 +16,8 @@
 #include <asm/arch/rcar-gen3-base.h>
 #elif defined(CONFIG_RCAR_GEN4)
 #include <asm/arch/rcar-gen4-base.h>
+#elif defined(CONFIG_RCAR_GEN5)
+#include <asm/arch/rcar-gen5-base.h>
 #elif defined(CONFIG_R7S72100)
 #elif defined(CONFIG_RZG2L)
 #include <asm/arch/rzg2l.h>
@@ -42,6 +44,7 @@
 #define RENESAS_CPU_TYPE_R8A779F0	0x5A
 #define RENESAS_CPU_TYPE_R8A779G0	0x5C
 #define RENESAS_CPU_TYPE_R8A779H0	0x5D
+#define RMOBILE_CPU_TYPE_R8A78000	0x60
 #define RENESAS_CPU_TYPE_R9A07G044L	0x9A070440

 #ifndef __ASSEMBLY__
--- a/arch/arm/mach-renesas/psci-rcar64.c
+++ b/arch/arm/mach-renesas/psci-rcar64.c
@@ -32,7 +32,12 @@ u32 __secure psci_version(void)

 void __secure __noreturn psci_system_reset(void)
 {
+#if defined(CONFIG_RCAR_GEN5)
+	writel(RST_KCPROT_DIS, RST_RESKCPROT0);
+	writel(0x1, RST_SWSRES1A);
+#else
 	writel(RST_SPRES, RST_SRESCR0);
+#endif

 	while (1)
 		;
--- a/arch/arm/mach-socfpga/config.mk
+++ b/arch/arm/mach-socfpga/config.mk
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Brian Sune <briansune@gmail.com>
+
+ifeq ($(CONFIG_TARGET_SOCFPGA_CYCLONE5),y)
+archprepare: socfpga_g5_handoff_prepare
+else ifeq ($(CONFIG_TARGET_SOCFPGA_ARRIA5),y)
+archprepare: socfpga_g5_handoff_prepare
+endif
+
+socfpga_g5_handoff_prepare:
+	@SOCFAMILY="$(SOCFAMILY)"; \
+		if [ -z "$$SOCFAMILY" ]; then \
+			exit 0; \
+		fi; \
+		echo "[INFO] SOC family detected: $$SOCFAMILY";
+		@set -- $$(awk -F'"' ' \
+		    /^CONFIG_SYS_VENDOR=/ {v=$$2} \
+		    /^CONFIG_SYS_BOARD=/ {b=$$2} \
+		    END {print v, b}' .config); \
+		VENDOR=$$1; \
+		BOARD=$$2; \
+		if [ -z "$$VENDOR" ] || [ -z "$$BOARD" ]; then \
+			exit 0; \
+		fi; \
+		BOARD_DIR=$(src)/board/$$VENDOR/$$BOARD; \
+		if [ "$$HANDOFF_PATH" ]; then \
+			echo "[INFO] Using manually specified handoff folder: $$HANDOFF_PATH"; \
+		else \
+			HANDOFF_BASE=$$BOARD_DIR/hps_isw_handoff; \
+			if [ ! -d "$$HANDOFF_BASE" ]; then \
+				exit 0; \
+			fi; \
+			HANDOFF_PATH=$$(ls -d "$$HANDOFF_BASE"/*/ 2>/dev/null | head -n1); \
+			if [ -z "$$HANDOFF_PATH" ]; then \
+				exit 0; \
+			fi; \
+			echo "[INFO] Auto-detected handoff folder: $$HANDOFF_PATH"; \
+		fi; \
+		HIOF_FILE=$$HANDOFF_PATH/$$(basename $$HANDOFF_PATH).hiof; \
+		if [ ! -f "$$HIOF_FILE" ]; then \
+			echo "[WARN] No .hiof file found in $$HANDOFF_PATH, skipping BSP generation."; \
+			exit 0; \
+		fi; \
+		echo "[INFO] Found hiof file: $$HIOF_FILE"; \
+		echo "[INFO] Running BSP generator..."; \
+		python3 $(src)/tools/cv_bsp_generator/cv_bsp_generator.py -i "$$HANDOFF_PATH" -o "$$BOARD_DIR/qts" || echo "[WARN] BSP generator failed, continuing..."; \
+		echo "[DONE] SoCFPGA QTS handoff conversion complete."
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -222,7 +222,7 @@ static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc,
 }

 U_BOOT_CMD(bridge, 3, 1, do_bridge,
-	   "SoCFPGA HPS FPGA bridge control",
+	   "GEN5 SoCFPGA HPS FPGA bridge control",
 	   "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges\n"
 	   "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges\n"
 	   ""
@@ -261,7 +261,16 @@ void socfpga_get_managers_addr(void)
 	if (ret)
 		hang();

-	else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X))
+	if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) &&
+	    !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) &&
+	    !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) {
+		ret = socfpga_get_base_addr("altr,sys-mgr",
+					    &socfpga_sysmgr_base);
+		if (ret)
+			hang();
+	}
+
+	if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X))
 		ret = socfpga_get_base_addr("intel,n5x-clkmgr",
 					    &socfpga_clkmgr_base);
 	else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) &&
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -217,6 +217,34 @@ int arch_early_init_r(void)
 static struct socfpga_sdr_ctrl *sdr_ctrl =
 	(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;

+void socfpga_sdram_apply_static_cfg(void)
+{
+	const u32 applymask = 0x8;
+	u32 val = readl(&sdr_ctrl->static_cfg) | applymask;
+
+	/*
+	 * SDRAM staticcfg register specific:
+	 * When applying the register setting, the CPU must not access
+	 * SDRAM. Luckily for us, we can use i-cache here to help us
+	 * circumvent the SDRAM access issue. The idea is to make sure
+	 * that the code is in one full i-cache line by branching past
+	 * it and back. Once it is in the i-cache, we execute the core
+	 * of the code and apply the register settings.
+	 *
+	 * The code below uses 7 instructions, while the Cortex-A9 has
+	 * 32-byte cachelines, thus the limit is 8 instructions total.
+	 */
+	asm volatile(".align	5			\n"
+		     "		b 2f			\n"
+		     "1: 	str %0,	[%1]		\n"
+		     "		dsb			\n"
+		     "		isb			\n"
+		     "		b 3f			\n"
+		     "2:	b 1b			\n"
+		     "3:	nop			\n"
+		    : : "r"(val), "r"(&sdr_ctrl->static_cfg) : "memory", "cc");
+}
+
 void do_bridge_reset(int enable, unsigned int mask)
 {
 	int i;
@@ -234,7 +262,10 @@ void do_bridge_reset(int enable, unsigned int mask)
 		writel(iswgrp_handoff[2],
 		       socfpga_get_sysmgr_addr() +
 		       SYSMGR_GEN5_FPGAINFGRP_MODULE);
-		writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
+		if (iswgrp_handoff[3]) {
+			writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
+			socfpga_sdram_apply_static_cfg();
+		}
 		writel(iswgrp_handoff[0],
 		       socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 		writel(iswgrp_handoff[1], &nic301_regs->remap);
@@ -246,6 +277,7 @@ void do_bridge_reset(int enable, unsigned int mask)
 		writel(0, socfpga_get_sysmgr_addr() +
 		       SYSMGR_GEN5_FPGAINFGRP_MODULE);
 		writel(0, &sdr_ctrl->fpgaport_rst);
+		socfpga_sdram_apply_static_cfg();
 		writel(0x7, socfpga_get_rstmgr_addr() + RSTMGR_GEN5_BRGMODRST);
 		writel(1, &nic301_regs->remap);
 	}
--- a/arch/sh/cpu/u-boot.lds
+++ b/arch/sh/cpu/u-boot.lds
@@ -72,6 +72,7 @@ SECTIONS

 	__u_boot_list : {
 		KEEP(*(SORT(__u_boot_list*)));
+		. = ALIGN(8);
 	} >ram

 	PROVIDE (__init_end = .);
@@ -83,7 +84,7 @@ SECTIONS
 	.bss :
 	{
 		*(.bss)
-		. = ALIGN(4);
+		. = ALIGN(8);
 	} >ram
 	PROVIDE (bss_end = .);
 	PROVIDE (__bss_end = .);
--- a/board/BuR/brppt1/MAINTAINERS
+++ b/board/BuR/brppt1/MAINTAINERS
@@ -1,9 +1,8 @@
 BRPPT1 BOARD
-M:	Wolfgang Wallner <wolfgang.wallner@br-automation.com>
+M:	Wolfgang Wallner <wolfgang.wallner@at.abb.com>
 S:	Maintained
 F:	board/BuR/brppt1/
 F:	board/BuR/common/
 F:	include/configs/brppt1.h
 F:	configs/brppt1_mmc_defconfig
-F:	configs/brppt1_nand_defconfig
-F:	configs/brppt1_spi_defconfig
+F:	arch/arm/dts/am335x-brppt1-mmc*
--- a/board/BuR/brppt2/MAINTAINERS
+++ b/board/BuR/brppt2/MAINTAINERS
@@ -1,7 +1,8 @@
 BUR_PPT2 BOARD
-M:	Wolfgang Wallner <wolfgang.wallner@br-automation.com>
+M:	Wolfgang Wallner <wolfgang.wallner@at.abb.com>
 S:	Maintained
 F:	board/BuR/brppt2/
 F:	board/BuR/common/
 F:	include/configs/brppt2.h
 F:	configs/brppt2_defconfig
+F:	arch/arm/dts/imx6dl-brppt2.dts
--- a/board/BuR/brsmarc1/MAINTAINERS
+++ b/board/BuR/brsmarc1/MAINTAINERS
@@ -1,7 +1,8 @@
 BRSMARC1 BOARD
-M:	Wolfgang Wallner <wolfgang.wallner@br-automation.com>
+M:	Wolfgang Wallner <wolfgang.wallner@at.abb.com>
 S:	Maintained
 F:	board/BuR/brsmarc1/
 F:	board/BuR/common/
 F:	include/configs/brsmarc1.h
 F:	configs/brsmarc1_defconfig
+F:	arch/arm/dts/am335x-brsmarc1.dts
--- a/board/BuR/brxre1/MAINTAINERS
+++ b/board/BuR/brxre1/MAINTAINERS
@@ -1,5 +1,5 @@
 BRXRE1 BOARD
-M:	Wolfgang Wallner <wolfgang.wallner@br-automation.com>
+M:	Wolfgang Wallner <wolfgang.wallner@at.abb.com>
 S:	Maintained
 F:	board/BuR/brxre1/
 F:	board/BuR/common/
--- a/board/BuR/zynq/MAINTAINERS
+++ b/board/BuR/zynq/MAINTAINERS
@@ -1,5 +1,5 @@
 ZYNQ BOARD
-M:	Wolfgang Wallner <wolfgang.wallner@br-automation.com>
+M:	Wolfgang Wallner <wolfgang.wallner@at.abb.com>
 S:	Maintained
 F:	board/BuR/zynq/
 F:	board/BuR/common/
--- a/board/armltd/integrator/MAINTAINERS
+++ b/board/armltd/integrator/MAINTAINERS
@@ -1,5 +1,5 @@
 INTEGRATOR BOARD
-M:	Linus Walleij <linus.walleij@linaro.org>
+M:	Linus Walleij <linusw@kernel.org>
 S:	Maintained
 F:	board/armltd/integrator/
 F:	include/configs/integratorcp.h
--- a/board/armltd/vexpress64/MAINTAINERS
+++ b/board/armltd/vexpress64/MAINTAINERS
@@ -1,18 +1,18 @@
 VEXPRESS64 PLATFORM
 M:	David Feng <fenghua@phytium.com.cn>
-M:	Linus Walleij <linus.walleij@linaro.org>
+M:	Linus Walleij <linusw@kernel.org>
 M:	Peter Hoyes <Peter.Hoyes@arm.com>
 S:	Maintained
 F:	board/armltd/vexpress64/
 F:	include/configs/vexpress_aemv8.h

 VEXPRESS_AEMV8A_SEMI BOARD
-M:	Linus Walleij <linus.walleij@linaro.org>
+M:	Linus Walleij <linusw@kernel.org>
 S:	Maintained
 F:	configs/vexpress_aemv8a_semi_defconfig

 JUNO DEVELOPMENT PLATFORM BOARD
-M:	Linus Walleij <linus.walleij@linaro.org>
+M:	Linus Walleij <linusw@kernel.org>
 S:	Maintained
 F:	configs/vexpress_aemv8a_juno_defconfig

--- a/board/broadcom/bcmns/MAINTAINERS
+++ b/board/broadcom/bcmns/MAINTAINERS
@@ -1,5 +1,5 @@
 BCMNS BOARD
-M:	Linus Walleij <linus.walleij@linaro.org>
+M:	Linus Walleij <linusw@kernel.org>
 S:	Maintained
 F:	board/broadcom/bcmns/
 F:	configs/bcmns_defconfig
--- a/board/raspberrypi/rpi/lowlevel_init.S
+++ b/board/raspberrypi/rpi/lowlevel_init.S
@@ -16,7 +16,8 @@ save_boot_params:

 	/* The firmware provided ATAG/FDT address can be found in r2/x0 */
 #ifdef CONFIG_ARM64
-	adr	x8, fw_dtb_pointer
+	adrp	x8, fw_dtb_pointer
+	add     x8, x8, #:lo12:fw_dtb_pointer
 	str	x0, [x8]
 #else
 	ldr	r8, =fw_dtb_pointer
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -3,6 +3,8 @@
 * (C) Copyright 2012-2016 Stephen Warren
 */

+#define LOG_CATEGORY	LOGC_BOARD
+
 #include <config.h>
 #include <dm.h>
 #include <env.h>
@@ -332,13 +334,27 @@ int dram_init(void)
 #ifdef CONFIG_OF_BOARD
 int dram_init_banksize(void)
 {
+	phys_addr_t total_size = 0;
+	int i;
 	int ret;

 	ret = fdtdec_setup_memory_banksize();
 	if (ret)
 		return ret;

-	return fdtdec_setup_mem_size_base();
+	ret = fdtdec_setup_mem_size_base();
+	if (ret)
+		return ret;
+
+	/* Update gd->ram_size to reflect total RAM across all banks */
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		if (gd->bd->bi_dram[i].size == 0)
+			break;
+		total_size += gd->bd->bi_dram[i].size;
+	}
+	gd->ram_size = total_size;
+
+	return 0;
 }
 #endif

@@ -354,15 +370,13 @@ static void set_fdtfile(void)
 }

 /*
- * If the firmware provided a valid FDT at boot time, let's expose it in
- * ${fdt_addr} so it may be passed unmodified to the kernel.
+ * Allow U-Boot to use its control FDT with extlinux if one is not provided.
+ * This will then go through the usual fixups that U-Boot does, before being
+ * handed off to Linux
 */
 static void set_fdt_addr(void)
 {
-	if (fdt_magic(fw_dtb_pointer) != FDT_MAGIC)
-		return;
-
-	env_set_hex("fdt_addr", fw_dtb_pointer);
+	env_set_hex("fdt_addr", (ulong)gd->fdt_blob);
 }

 /*
@@ -608,7 +622,10 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 {
 	int node;

-	update_fdt_from_fw(blob, (void *)fw_dtb_pointer);
+	if (blob == gd->fdt_blob)
+		log_debug("Same FDT: nothing to do\n");
+	else
+		update_fdt_from_fw(blob, (void *)gd->fdt_blob);

 	if (CONFIG_IS_ENABLED(FDT_SIMPLEFB)) {
 		node = fdt_node_offset_by_compatible(blob, -1, "simple-framebuffer");
--- a/board/renesas/MAINTAINERS
+++ b/board/renesas/MAINTAINERS
@@ -6,7 +6,7 @@ N:	grpeach
 N:	r2dplus
 N:	r7s72100
 N:	r8a66597
-N:	r8a77
+N:	r8a7[78]
 N:	r9a0[0-9]g
 N:	rcar
 N:	renesas
--- a/board/renesas/common/Makefile
+++ b/board/renesas/common/Makefile
@@ -43,6 +43,10 @@ else
 obj-y	+= gen4-common.o
 endif
 endif
+
+ifdef CONFIG_RCAR_GEN5
+obj-y	+= gen5-common.o
+endif
 endif

 endif
--- a/board/renesas/common/gen5-common.c
+++ b/board/renesas/common/gen5-common.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 Renesas Electronics Corp.
+ */
+
+#include <asm/arch/renesas.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/processor.h>
+#include <asm/system.h>
+#include <linux/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void init_generic_timer(void)
+{
+	const u32 freq = CONFIG_SYS_CLK_FREQ;
+
+	/* Update memory mapped and register based freqency */
+	asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
+	writel(freq, CNTFID0);
+
+	/* Enable counter */
+	setbits_le32(CNTCR_BASE, CNTCR_EN);
+}
+
+static void init_gic_v3(void)
+{
+	/* GIC v3 power on */
+	writel(BIT(1), GICR_LPI_PWRR);
+
+	/* Wait till the WAKER_CA_BIT changes to 0 */
+	clrbits_le32(GICR_LPI_WAKER, BIT(1));
+	while (readl(GICR_LPI_WAKER) & BIT(2))
+		;
+
+	writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
+}
+
+void s_init(void)
+{
+	if (current_el() == 3)
+		init_generic_timer();
+}
+
+int board_early_init_f(void)
+{
+	return 0;
+}
+
+int board_init(void)
+{
+	/* Allow WDT reset */
+	writel(RST_KCPROT_DIS, RST_RESKCPROT0);
+	clrbits_le32(RST_WDTRSTCR, RST_WWDT_RSTMSK | RST_RWDT_RSTMSK);
+
+	if (current_el() != 3)
+		return 0;
+	init_gic_v3();
+
+	return 0;
+}
+
+void __weak reset_cpu(void)
+{
+	writel(RST_KCPROT_DIS, RST_RESKCPROT0);
+	writel(0x1, RST_SWSRES1A);
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
--- a/board/renesas/ironhide/Kconfig
+++ b/board/renesas/ironhide/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IRONHIDE
+
+config SYS_SOC
+	default "renesas"
+
+config SYS_BOARD
+	default "ironhide"
+
+config SYS_VENDOR
+	default "renesas"
+
+config SYS_CONFIG_NAME
+	default "ironhide"
+
+endif
--- a/board/samsung/e850-96/Makefile
+++ b/board/samsung/e850-96/Makefile
@@ -3,4 +3,4 @@
 # Copyright (C) 2024, Linaro Limited
 # Sam Protsenko <semen.protsenko@linaro.org>

-obj-y := e850-96.o fw.o acpm.o pmic.o
+obj-y := e850-96.o fw.o acpm.o pmic.o bootdev.o
--- a/board/samsung/e850-96/bootdev.c
+++ b/board/samsung/e850-96/bootdev.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025 Linaro Ltd.
+ * Author: Sam Protsenko <semen.protsenko@linaro.org>
+ *
+ * Routines for checking current boot device.
+ */
+
+#include <linux/arm-smccc.h>
+#include <vsprintf.h>
+#include "bootdev.h"
+
+/* Flag from BL2 bootloader in RAM */
+#define BL2_TAG_ADDR			0x80000000	/* DRAM base */
+#define BL2_TAG				0xabcdef
+
+/* Boot device info location in iRAM (only accessible from EL3) */
+#define IRAM_BASE			0x02020000
+#define BOOTDEVICE_INFO_ADDR		(IRAM_BASE + 0x64)
+
+/* SMC call for getting boot device information from EL3 monitor */
+#define SMC_CMD_CHECK_SECOND_BOOT	-233
+
+/* Boot device constants for the encoded boot device info value */
+#define BD_NO_DEVICE			0x0
+#define BD_UFS				0x1
+#define BD_EMMC				0x2
+#define BD_ERROR			0x3
+#define BD_USB				0x4
+#define BD_SDMMC			0x5
+#define BD_UFS_CARD			0x6
+#define BD_SPI				0x7
+
+/* If BL2 bootloader wasn't executed, it means U-Boot is running via JTAG */
+static bool bootdev_is_jtag_session(void)
+{
+	u32 bl2_tag_val = *(u32 *)BL2_TAG_ADDR;
+
+	return bl2_tag_val != BL2_TAG;
+}
+
+/* Obtain boot device information encoded in 32-bit value */
+static u32 bootdev_get_info(void)
+{
+	u32 info;
+
+	/*
+	 * On regular boot U-Boot is executed by BL2 bootloader, and is running
+	 * in EL1 mode, so the boot device information has to be obtained via
+	 * SMC call from EL3 software (EL3 monitor), which can read that info
+	 * from the protected iRAM memory. If U-Boot is running via TRACE32 JTAG
+	 * (in EL3 mode), read the boot device info directly from iRAM, as EL3
+	 * software might not be available.
+	 */
+	if (bootdev_is_jtag_session()) {
+		info = *(u32 *)BOOTDEVICE_INFO_ADDR;
+	} else {
+		struct arm_smccc_res res;
+
+		arm_smccc_smc(SMC_CMD_CHECK_SECOND_BOOT, 0, 0, 0, 0, 0, 0, 0,
+			      &res);
+		info = (u32)res.a2;
+	}
+
+	return info;
+}
+
+enum bootdev bootdev_get_current(void)
+{
+	u32 info, magic, order, dev;
+
+	info = bootdev_get_info();
+	magic = info >> 24;
+	order = info & 0xf;
+	dev = (info >> (4 * order)) & 0xf;
+
+	if (magic != 0xcb)
+		panic("Abnormal boot");
+
+	switch (dev) {
+	case BD_UFS:
+		return BOOTDEV_UFS;
+	case BD_EMMC:
+		return BOOTDEV_EMMC;
+	case BD_USB:
+		return BOOTDEV_USB;
+	case BD_SDMMC:
+		return BOOTDEV_SD;
+	default:
+		return BOOTDEV_ERROR;
+	}
+
+	return BOOTDEV_ERROR;
+}
+
+bool bootdev_is_usb(void)
+{
+	return bootdev_get_current() == BOOTDEV_USB;
+}
--- a/board/samsung/e850-96/bootdev.h
+++ b/board/samsung/e850-96/bootdev.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2025 Linaro Ltd.
+ * Sam Protsenko <semen.protsenko@linaro.org>
+ */
+
+#ifndef __E850_96_BOOTDEV_H
+#define __E850_96_BOOTDEV_H
+
+#include <stdbool.h>
+
+enum bootdev {
+	BOOTDEV_ERROR,
+	BOOTDEV_SD,
+	BOOTDEV_EMMC,
+	BOOTDEV_USB,
+	BOOTDEV_UFS,
+};
+
+enum bootdev bootdev_get_current(void);
+bool bootdev_is_usb(void);
+
+#endif /* __E850_96_BOOTDEV_H */
--- a/board/samsung/e850-96/e850-96.c
+++ b/board/samsung/e850-96/e850-96.c
@@ -11,6 +11,7 @@
 #include <net.h>
 #include <usb.h>
 #include <asm/io.h>
+#include "bootdev.h"
 #include "fw.h"
 #include "pmic.h"

@@ -31,6 +32,10 @@
 #define EMMC_DEV_NUM			0
 #define EMMC_ESP_PART			1

+/* Firmware size */
+#define LDFW_MAX_SIZE			SZ_4M
+#define SP_MAX_SIZE			SZ_1M
+
 struct efi_fw_image fw_images[] = {
 	{
 		.image_type_id = E850_96_FWBL1_IMAGE_GUID,
@@ -77,16 +82,6 @@ static struct acpm acpm = {
 	.ipc_ch		= EXYNOS850_IPC_AP_I3C,
 };

-int dram_init(void)
-{
-	return fdtdec_setup_mem_size_base();
-}
-
-int dram_init_banksize(void)
-{
-	return fdtdec_setup_memory_banksize();
-}
-
 /* Read the unique SoC ID from OTP registers */
 static u64 get_chip_id(void)
 {
@@ -137,11 +132,34 @@ static void setup_ethaddr(void)
 		eth_env_set_enetaddr("ethaddr", mac_addr);
 }

+static void load_firmware_usb(void)
+{
+	int err;
+
+	printf("Loading LDFW firmware (over USB)...\n");
+	err = load_image_usb(USB_DN_IMAGE_LDFW, LDFW_NWD_ADDR, LDFW_MAX_SIZE);
+	if (err) {
+		printf("ERROR: LDFW loading failed (%d)\n", err);
+		return;
+	}
+
+	err = init_ldfw(LDFW_NWD_ADDR);
+	if (err) {
+		printf("ERROR: LDFW init failed (%d)\n", err);
+		/* Do not return, still need to download SP */
+	}
+
+	printf("Loading SP firmware (over USB)...\n");
+	err = load_image_usb(USB_DN_IMAGE_SP, LDFW_NWD_ADDR, SP_MAX_SIZE);
+	if (err)
+		printf("ERROR: SP loading failed (%d)\n", err);
+}
+
 /*
 * Call this in board_late_init() to avoid probing block devices before
 * efi_init_early().
 */
-void load_firmware(void)
+static void load_firmware_blk(void)
 {
 	const char *ifname;
 	ulong dev, part;
@@ -161,16 +179,41 @@ void load_firmware(void)
 	}

 	printf("Loading LDFW firmware (from %s %ld)...\n", ifname, dev);
-	err = load_ldfw(ifname, dev, part, LDFW_NWD_ADDR);
-	if (err)
+	err = load_ldfw_from_blk(ifname, dev, part, LDFW_NWD_ADDR);
+	if (err) {
 		printf("ERROR: LDFW loading failed (%d)\n", err);
+		return;
+	}
+	err = init_ldfw(LDFW_NWD_ADDR);
+	if (err)
+		printf("ERROR: LDFW init failed (%d)\n", err);
+}
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+	return fdtdec_setup_memory_banksize();
 }

 int board_late_init(void)
 {
 	setup_serial();
 	setup_ethaddr();
-	load_firmware();
+
+	if (bootdev_is_usb())
+		load_firmware_usb();
+	else
+		load_firmware_blk();
+
+	if (bootdev_is_usb()) {
+		env_set("bootcmd", "echo \"Entering DFU mode...\"; "
+			"dfu 0 mmc 0");
+		env_set("bootdelay", "0");
+	}

 	return 0;
 }
--- a/board/samsung/e850-96/fw.c
+++ b/board/samsung/e850-96/fw.c
@@ -11,14 +11,19 @@
 #include <linux/arm-smccc.h>
 #include "fw.h"

-#define LDFW_RAW_PART		"ldfw"
-#define LDFW_FAT_PATH		"/EFI/firmware/ldfw.bin"
+#define LDFW_RAW_PART			"ldfw"
+#define LDFW_FAT_PATH			"/EFI/firmware/ldfw.bin"
+#define LDFW_MAGIC			0x10adab1e

-#define LDFW_MAGIC		0x10adab1e
-#define SMC_CMD_LOAD_LDFW	-0x500
-#define SDM_HW_RESET_STATUS	0x1230
-#define SDM_SW_RESET_STATUS	0x1231
-#define SB_ERROR_PREFIX		0xfdaa0000
+/* SMC command for providing LDFW to EL3 monitor */
+#define SMC_CMD_LOAD_LDFW		-0x500
+/* SMC command for loading some binary over USB */
+#define SMC_CMD_LOAD_IMAGE_BY_USB	-0x512
+
+/* Error codes for SMC_CMD_LOAD_LDFW */
+#define SDM_HW_RESET_STATUS		0x1230
+#define SDM_SW_RESET_STATUS		0x1231
+#define SB_ERROR_PREFIX			0xfdaa0000

 struct ldfw_header {
 	u32 magic;
@@ -94,7 +99,27 @@ static int read_fw_from_raw(const char *ifname, int dev, const char *part_name,
 }

 /**
- * load_ldfw - Load the loadable firmware (LDFW)
+ * load_image_usb - Load some binary over USB during USB boot
+ * @type: Image type
+ * @addr: Memory address where the image should be downloaded to
+ * @size: Image size
+ *
+ * Return: 0 on success or a negative value on error.
+ */
+int load_image_usb(enum usb_dn_image type, phys_addr_t addr, phys_size_t size)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(SMC_CMD_LOAD_IMAGE_BY_USB, (u64)type, addr, size,
+		      0, 0, 0, 0, &res);
+	if (res.a0)
+		return -EIO;
+
+	return 0;
+}
+
+/**
+ * load_ldfw_from_blk - Load the loadable firmware (LDFW) from block device
 * @ifname: Interface name of the block device to load the firmware from
 * @dev: Device number
 * @part: Partition number
@@ -102,24 +127,37 @@ static int read_fw_from_raw(const char *ifname, int dev, const char *part_name,
 *
 * Return: 0 on success or a negative value on error.
 */
-int load_ldfw(const char *ifname, int dev, int part, phys_addr_t addr)
+int load_ldfw_from_blk(const char *ifname, int dev, int part, phys_addr_t addr)
 {
-	struct ldfw_header *hdr;
-	struct arm_smccc_res res;
 	void *buf = (void *)addr;
-	u64 size = 0;
-	int err, i;
+	int err;

 	/* First try to read LDFW from EFI partition, then from the raw one */
 	err = read_fw_from_fat(ifname, dev, part, LDFW_FAT_PATH, buf);
-	if (err) {
-		err = read_fw_from_raw(ifname, dev, LDFW_RAW_PART, buf);
-		if (err)
-			return err;
-	}
+	if (err)
+		return read_fw_from_raw(ifname, dev, LDFW_RAW_PART, buf);
+
+	return 0;
+}
+
+/**
+ * init_ldfw - Provide the LDFW (loaded to RAM) to EL3 monitor to make use of it
+ * @addr: Memory address where LDFW resides
+ *
+ * EL3 monitor will copy the LDFW from the provided Normal World memory @addr to
+ * Secure World location, and start using it.
+ *
+ * Return: 0 on success or a negative value on error.
+ */
+int init_ldfw(phys_addr_t addr)
+{
+	struct ldfw_header *hdr;
+	struct arm_smccc_res res;
+	u64 size = 0;
+	int err, i;

 	/* Validate LDFW by magic number in its header */
-	hdr = buf;
+	hdr = (struct ldfw_header *)addr;
 	if (hdr->magic != LDFW_MAGIC) {
 		debug("%s: Wrong LDFW magic; is LDFW flashed?\n", __func__);
 		return -EINVAL;
--- a/board/samsung/e850-96/fw.h
+++ b/board/samsung/e850-96/fw.h
@@ -9,6 +9,14 @@

 #include <asm/types.h>

-int load_ldfw(const char *ifname, int dev, int part, phys_addr_t addr);
+/* Image types for downloading over USB */
+enum usb_dn_image {
+	USB_DN_IMAGE_LDFW	= 1,	/* Loadable Firmware */
+	USB_DN_IMAGE_SP		= 2,	/* Secure Payload (tzsw.img) */
+};
+
+int load_image_usb(enum usb_dn_image type, phys_addr_t addr, phys_size_t size);
+int load_ldfw_from_blk(const char *ifname, int dev, int part, phys_addr_t addr);
+int init_ldfw(phys_addr_t addr);

 #endif /* __E850_96_FW_H */
--- a/board/samsung/exynos-mobile/Kconfig
+++ b/board/samsung/exynos-mobile/Kconfig
@@ -0,0 +1,18 @@
+if TARGET_EXYNOS_MOBILE
+
+config ENV_SOURCE_FILE
+	default "exynos-mobile"
+
+config LNX_KRNL_IMG_TEXT_OFFSET_BASE
+	default TEXT_BASE
+
+config SYS_BOARD
+	default "exynos-mobile"
+
+config SYS_CONFIG_NAME
+	default "exynos-mobile"
+
+config SYS_VENDOR
+	default "samsung"
+
+endif # TARGET_EXYNOS_MOBILE
--- a/board/samsung/exynos-mobile/MAINTAINERS
+++ b/board/samsung/exynos-mobile/MAINTAINERS
@@ -0,0 +1,6 @@
+Exynos Generic Boards (for mobile devices)
+M:	Kaustabh Chakraborty <kauschluss@disroot.org>
+S:	Maintained
+F:	board/samsung/exynos-mobile/
+F:	configs/exynos-mobile_defconfig
+F:	include/configs/exynos-mobile.h
--- a/board/samsung/exynos-mobile/Makefile
+++ b/board/samsung/exynos-mobile/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2025 Kaustabh Chakraborty <kauschluss@disroot.org>
+
+obj-y := exynos-mobile.o
--- a/board/samsung/exynos-mobile/debug-exynos7870.config
+++ b/board/samsung/exynos-mobile/debug-exynos7870.config
@@ -0,0 +1,7 @@
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x13820000
+CONFIG_DEBUG_UART_CLOCK=133250000
+CONFIG_DEBUG_UART_S5P=y
+CONFIG_LOG=y
+CONFIG_LOG_CONSOLE=y
+CONFIG_LOG_MAX_LEVEL=8
--- a/board/samsung/exynos-mobile/exynos-mobile.c
+++ b/board/samsung/exynos-mobile/exynos-mobile.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Samsung Exynos Generic Board Source (for mobile devices)
+ *
+ * Copyright (c) 2025 Kaustabh Chakraborty <kauschluss@disroot.org>
+ */
+
+#include <asm/armv8/mmu.h>
+#include <blk.h>
+#include <bootflow.h>
+#include <ctype.h>
+#include <dm/ofnode.h>
+#include <env.h>
+#include <errno.h>
+#include <init.h>
+#include <limits.h>
+#include <linux/sizes.h>
+#include <lmb.h>
+#include <part.h>
+#include <stdbool.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define lmb_alloc(size, addr) \
+	lmb_alloc_mem(LMB_MEM_ALLOC_ANY, SZ_2M, addr, size, LMB_NONE)
+
+struct exynos_board_info {
+	const char *name;
+	const char *chip;
+	const u64 *const dram_bank_bases;
+
+	char serial[64];
+
+	int (*const match)(struct exynos_board_info *);
+	const char *match_model;
+	const u8 match_max_rev;
+};
+
+/*
+ * The memory mapping includes all DRAM banks, along with the
+ * peripheral block, and a sentinel at the end. This is filled in
+ * dynamically.
+ */
+static struct mm_region exynos_mem_map[CONFIG_NR_DRAM_BANKS + 2] = {
+	{
+		/* Peripheral MMIO block */
+		.virt = 0x10000000UL,
+		.phys = 0x10000000UL,
+		.size = 0x10000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+	},
+};
+
+struct mm_region *mem_map = exynos_mem_map;
+
+static const u64 exynos7870_common_dram_bank_bases[CONFIG_NR_DRAM_BANKS] = {
+	0x40000000, 0x80000000, 0x100000000,
+};
+
+static const char *exynos_prev_bl_get_bootargs(void)
+{
+	void *prev_bl_fdt_base = (void *)get_prev_bl_fdt_addr();
+	int chosen_node_offset, ret;
+	const struct fdt_property *bootargs_prop;
+
+	ret = fdt_check_header(prev_bl_fdt_base);
+	if (ret < 0) {
+		log_err("%s: FDT is invalid (FDT_ERR %d)\n", __func__, ret);
+		return NULL;
+	}
+
+	ret = fdt_path_offset(prev_bl_fdt_base, "/chosen");
+	chosen_node_offset = ret;
+	if (ret < 0) {
+		log_err("%s: /chosen node not found (FDT_ERR %d)\n", __func__,
+			ret);
+		return NULL;
+	}
+
+	bootargs_prop = fdt_get_property(prev_bl_fdt_base, chosen_node_offset,
+					 "bootargs", &ret);
+	if (!bootargs_prop) {
+		log_err("%s: /chosen/bootargs property not found (FDT_ERR %d)\n",
+			__func__, ret);
+		return NULL;
+	}
+
+	return bootargs_prop->data;
+}
+
+static int exynos7870_fdt_match(struct exynos_board_info *board_info)
+{
+	const char *prev_bl_bootargs;
+	int val, ret;
+
+	prev_bl_bootargs = exynos_prev_bl_get_bootargs();
+	if (!prev_bl_bootargs)
+		return -1;
+
+	/*
+	 * Read the cmdline property which stores the
+	 * bootloader/firmware version. An example value of the option
+	 * can be: "J600GDXU3ARH5". This can be used to verify the model
+	 * of the device.
+	 */
+	ret = cmdline_get_arg(prev_bl_bootargs, "androidboot.bootloader", &val);
+	if (ret < 0) {
+		log_err("%s: unable to find property for bootloader version (%d)\n",
+			__func__, ret);
+		return -1;
+	}
+
+	if (strncmp(prev_bl_bootargs + val, board_info->match_model,
+		    strlen(board_info->match_model)))
+		return -1;
+
+	/*
+	 * Read the cmdline property which stores the hardware revision.
+	 * This is required to allow selecting one of multiple dtbs
+	 * available of a single device, varying in hardware changes in
+	 * different revisions.
+	 */
+	ret = cmdline_get_arg(prev_bl_bootargs, "androidboot.revision", &val);
+	if (ret < 0)
+		ret = cmdline_get_arg(prev_bl_bootargs, "androidboot.hw_rev", &val);
+	if (ret < 0) {
+		log_err("%s: unable to find property for bootloader revision (%d)\n",
+			__func__, ret);
+		return -1;
+	}
+
+	if (strtoul(prev_bl_bootargs + val, NULL, 10) > board_info->match_max_rev)
+		return -1;
+
+	/*
+	 * Read the cmdline property which stores the serial number.
+	 * Store this in the board info struct.
+	 */
+	ret = cmdline_get_arg(prev_bl_bootargs, "androidboot.serialno", &val);
+	if (ret > 0)
+		strlcpy(board_info->serial, prev_bl_bootargs + val, ret);
+
+	return 0;
+}
+
+/*
+ * This array is used for matching the models and revisions with the
+ * devicetree used by U-Boot. This allows a single U-Boot to work on
+ * multiple devices.
+ *
+ * Entries are kept in lexicographical order of board SoCs, followed by
+ * board names.
+ */
+static struct exynos_board_info exynos_board_info_match[] = {
+	{
+		/* Samsung Galaxy A2 Core */
+		.name = "a2corelte",
+		.chip = "exynos7870",
+		.dram_bank_bases = exynos7870_common_dram_bank_bases,
+		.match = exynos7870_fdt_match,
+		.match_model = "A260",
+		.match_max_rev = U8_MAX,
+	}, {
+		/* Samsung Galaxy J6 */
+		.name = "j6lte",
+		.chip = "exynos7870",
+		.dram_bank_bases = exynos7870_common_dram_bank_bases,
+		.match = exynos7870_fdt_match,
+		.match_model = "J600",
+		.match_max_rev = U8_MAX,
+	}, {
+		/* Samsung Galaxy J7 Prime */
+		.name = "on7xelte",
+		.chip = "exynos7870",
+		.dram_bank_bases = exynos7870_common_dram_bank_bases,
+		.match = exynos7870_fdt_match,
+		.match_model = "G610",
+		.match_max_rev = U8_MAX,
+	},
+};
+
+static void exynos_parse_dram_banks(const struct exynos_board_info *board_info,
+				    const void *fdt_base)
+{
+	u64 mem_addr, mem_size = 0;
+	u32 na, ns, i, j;
+	int offset;
+
+	if (fdt_check_header(fdt_base) < 0)
+		return;
+
+	/* #address-cells and #size-cells as defined in the fdt root. */
+	na = fdt_address_cells(fdt_base, 0);
+	ns = fdt_size_cells(fdt_base, 0);
+
+	fdt_for_each_subnode(offset, fdt_base, 0) {
+		if (strncmp(fdt_get_name(fdt_base, offset, NULL), "memory", 6))
+			continue;
+
+		for (i = 0; ; i++) {
+			mem_addr = fdtdec_get_addr_size_fixed(fdt_base, offset,
+							      "reg", i, na, ns,
+							      &mem_size, false);
+			if (mem_addr == FDT_ADDR_T_NONE)
+				break;
+
+			if (!mem_size)
+				continue;
+
+			for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) {
+				if (board_info->dram_bank_bases[j] != mem_addr)
+					continue;
+
+				mem_map[j + 1].phys = mem_addr;
+				mem_map[j + 1].virt = mem_addr;
+				mem_map[j + 1].size = mem_size;
+				mem_map[j + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+						       PTE_BLOCK_INNER_SHARE;
+				break;
+			}
+		}
+	}
+}
+
+static int exynos_fastboot_setup(void)
+{
+	struct blk_desc *blk_dev;
+	struct disk_partition info = {0};
+	char buf[128];
+	phys_addr_t addr;
+	int offset, i, j;
+
+	/* Allocate and define buffer address for fastboot interface. */
+	if (lmb_alloc(CONFIG_FASTBOOT_BUF_SIZE, &addr)) {
+		log_err("%s: failed to allocate fastboot buffer\n", __func__);
+		return -ENOMEM;
+	}
+	env_set_hex("fastboot_addr_r", addr);
+
+	blk_dev = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+	if (!blk_dev) {
+		log_err("%s: required mmc device not available\n", __func__);
+		return -ENODEV;
+	}
+
+	strcpy(buf, "fastboot_partition_alias_");
+	offset = strlen(buf);
+
+	for (i = 1; i < CONFIG_EFI_PARTITION_ENTRIES_NUMBERS; i++) {
+		if (part_get_info(blk_dev, i, &info))
+			continue;
+
+		/*
+		 * The partition name must be lowercase (stored in buf[]),
+		 * as is expected in all fastboot partitions ...
+		 */
+		strlcpy(buf + offset, info.name, sizeof(buf) - offset);
+		for (j = offset; buf[j]; j++)
+			buf[j] = tolower(buf[j]);
+		if (!strcmp(buf + offset, info.name))
+			continue;
+		/*
+		 * ... However, if that isn't the case, a fastboot
+		 * partition alias must be defined to establish it.
+		 */
+		env_set(buf, info.name);
+	}
+
+	return 0;
+}
+
+int board_fit_config_name_match(const char *name)
+{
+	struct exynos_board_info *board_info;
+	char buf[128];
+	unsigned int i;
+	int ret;
+
+	/*
+	 * Iterate over exynos_board_info_match[] to select the
+	 * appropriate board info struct. If not found, exit.
+	 */
+	for (i = 0; i < ARRAY_SIZE(exynos_board_info_match); i++) {
+		board_info = exynos_board_info_match + i;
+		snprintf(buf, sizeof(buf), "%s-%s", board_info->chip,
+			 board_info->name);
+
+		if (!strcmp(name, buf))
+			break;
+	}
+	if (i == ARRAY_SIZE(exynos_board_info_match))
+		return -1;
+
+	/*
+	 * Execute match logic for the target board. This is separated
+	 * as the process may be different for multiple boards.
+	 */
+	ret = board_info->match(board_info);
+	if (ret)
+		return ret;
+
+	/*
+	 * Store the correct board info struct in gd->board_type to
+	 * allow other functions to access it.
+	 */
+	gd->board_type = (ulong)board_info;
+	log_debug("%s: device detected: %s\n", __func__, name);
+
+	return 0;
+}
+
+int timer_init(void)
+{
+	ofnode timer_node;
+
+	/*
+	 * In a lot of Exynos devices, the previous bootloader does not
+	 * set CNTFRQ_EL0 properly. However, the timer node in
+	 * devicetree has the correct frequency, use that instead.
+	 */
+	timer_node = ofnode_by_compatible(ofnode_null(), "arm,armv8-timer");
+	gd->arch.timer_rate_hz = ofnode_read_u32_default(timer_node,
+							 "clock-frequency", 0);
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	const struct exynos_board_info *board_info;
+
+	if (!gd->board_type)
+		return -ENODATA;
+	board_info = (const struct exynos_board_info *)gd->board_type;
+
+	exynos_parse_dram_banks(board_info, gd->fdt_blob);
+	/*
+	 * Some devices have multiple variants based on the amount of
+	 * memory and internal storage. The lowest bank base has been
+	 * observed to have the same memory range in all board variants.
+	 * For variants with more memory, the previous bootloader should
+	 * overlay the devicetree with the required extra memory ranges.
+	 */
+	exynos_parse_dram_banks(board_info, (const void *)get_prev_bl_fdt_addr());
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	unsigned int i;
+
+	/* Select the largest RAM bank for U-Boot. */
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		if (gd->ram_size < mem_map[i + 1].size) {
+			gd->ram_base = mem_map[i + 1].phys;
+			gd->ram_size = mem_map[i + 1].size;
+		}
+	}
+
+	return 0;
+}
+
+int dram_init_banksize(void)
+{
+	unsigned int i;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = mem_map[i + 1].phys;
+		gd->bd->bi_dram[i].size = mem_map[i + 1].size;
+	}
+
+	return 0;
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	const struct exynos_board_info *board_info;
+	char buf[128];
+
+	if (!gd->board_type)
+		return -ENODATA;
+	board_info = (const struct exynos_board_info *)gd->board_type;
+
+	env_set("platform", board_info->chip);
+	env_set("board", board_info->name);
+
+	if (strlen(board_info->serial))
+		env_set("serial#", board_info->serial);
+
+	/* EFI booting requires the path to correct dtb, specify it here. */
+	snprintf(buf, sizeof(buf), "exynos/%s-%s.dtb", board_info->chip,
+		 board_info->name);
+	env_set("fdtfile", buf);
+
+	return exynos_fastboot_setup();
+}
--- a/board/samsung/exynos-mobile/exynos-mobile.env
+++ b/board/samsung/exynos-mobile/exynos-mobile.env
@@ -0,0 +1,18 @@
+stdin=serial,button-kbd
+stdout=serial,vidconsole
+stderr=serial,vidconsole
+
+bootdelay=0
+bootcmd=bootefi bootmgr; pause; bootmenu
+
+fastbootcmd=echo "Fastboot Mode";
+	fastboot -l $fastboot_addr_r usb 0
+
+bootmenu_0=Continue Boot=boot
+bootmenu_1=Enter Fastboot Mode=run fastbootcmd
+bootmenu_2=UEFI Maintenance Menu=eficonfig
+bootmenu_3=Reboot=reset
+bootmenu_4=Power Off=poweroff
+
+button_cmd_0_name=Volume Down Key
+button_cmd_0=bootmenu
--- a/board/softing/vining_fpga/socfpga.c
+++ b/board/softing/vining_fpga/socfpga.c
@@ -8,7 +8,7 @@
 #include <env.h>
 #include <init.h>
 #include <net.h>
-#include <status_led.h>
+#include <led.h>
 #include <asm/arch/reset_manager.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
@@ -24,10 +24,16 @@ DECLARE_GLOBAL_DATA_PTR;
 int board_late_init(void)
 {
 	const unsigned int usb_nrst_gpio = 35;
+	struct udevice *dev;
 	int ret;

-	status_led_set(1, CONFIG_LED_STATUS_ON);
-	status_led_set(2, CONFIG_LED_STATUS_ON);
+	ret = led_get_by_label("status_1", &dev);
+	if (!ret)
+		led_set_state(dev, LEDST_ON);
+
+	ret = led_get_by_label("status_2", &dev);
+	if (!ret)
+		led_set_state(dev, LEDST_ON);

 	/* Address of boot parameters for ATAG (if ATAG is used) */
 	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -429,7 +429,7 @@ void scale_vcores_generic(int freq)
 {
 	int sil_rev, mpu_vdd;

-	if (!IS_ENABLED(CONFIG_DM_PMIC_TPS65910))
+	if (!IS_ENABLED(CONFIG_SPL_POWER_TPS65910))
 		return;

 	/*
--- a/board/ti/am62x/evm.c
+++ b/board/ti/am62x/evm.c
@@ -82,11 +82,16 @@ struct efi_capsule_update_info update_info = {
 };

 #if CONFIG_IS_ENABLED(TI_I2C_BOARD_DETECT)
+int do_board_detect(void)
+{
+	return do_board_detect_am6();
+}
+
 int checkboard(void)
 {
 	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;

-	if (!do_board_detect_am6())
+	if (!do_board_detect())
 		printf("Board: %s rev %s\n", ep->name, ep->version);

 	return 0;
@@ -97,7 +102,7 @@ static void setup_board_eeprom_env(void)
 {
 	char *name = "am62x_skevm";

-	if (do_board_detect_am6())
+	if (do_board_detect())
 		goto invalid_eeprom;

 	if (board_is_am62x_skevm())
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -114,11 +114,16 @@ void spl_perform_board_fixups(struct spl_image_info *spl_image)
 #endif

 #ifdef CONFIG_TI_I2C_BOARD_DETECT
+int do_board_detect(void)
+{
+	return do_board_detect_am6();
+}
+
 int checkboard(void)
 {
 	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;

-	if (!do_board_detect_am6())
+	if (!do_board_detect())
 		printf("Board: %s rev %s\n", ep->name, ep->version);

 	return 0;
@@ -135,7 +140,7 @@ static void setup_board_eeprom_env(void)
 {
 	char *name = "am64x_gpevm";

-	if (do_board_detect_am6())
+	if (do_board_detect())
 		goto invalid_eeprom;

 	if (board_is_am64x_gpevm())
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -72,11 +72,16 @@ int board_fit_config_name_match(const char *name)
 #endif

 #ifdef CONFIG_TI_I2C_BOARD_DETECT
+int do_board_detect(void)
+{
+	return do_board_detect_am6();
+}
+
 int checkboard(void)
 {
 	struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;

-	if (do_board_detect_am6())
+	if (do_board_detect())
 		/* EEPROM not populated */
 		printf("Board: %s rev %s\n", "AM6-COMPROCEVM", "E3");
 	else
@@ -89,7 +94,7 @@ static void setup_board_eeprom_env(void)
 {
 	char *name = "am65x";

-	if (do_board_detect_am6())
+	if (do_board_detect())
 		goto invalid_eeprom;

 	if (board_is_am65x_base_board())
--- a/board/ti/common/board_detect.c
+++ b/board/ti/common/board_detect.c
@@ -825,7 +825,7 @@ bool __maybe_unused board_ti_was_eeprom_read(void)
 		return false;
 }

-#if CONFIG_IS_ENABLED(TI_I2C_BOARD_DETECT)
+#if IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)
 int do_board_detect_am6(void)
 {
 	int ret;
--- a/board/ti/omap3evm/MAINTAINERS
+++ b/board/ti/omap3evm/MAINTAINERS
@@ -1,5 +1,5 @@
 EVM BOARD
-M:	Derald D. Woods <woods.technical@gmail.com>
+M:	Tom Rini <trini@konsulko.com>
 S:	Maintained
 F:	board/ti/omap3evm/
 F:	include/configs/omap3_evm.h
--- a/boot/bootmeth_rauc.c
+++ b/boot/bootmeth_rauc.c
@@ -17,6 +17,7 @@
 #include <fs.h>
 #include <malloc.h>
 #include <mapmem.h>
+#include <part.h>
 #include <string.h>
 #include <linux/stringify.h>
 #include <asm/cache.h>
@@ -98,6 +99,7 @@ static int distro_rauc_scan_parts(struct bootflow *bflow)
 	struct distro_rauc_priv *priv;
 	char *boot_order;
 	const char **boot_order_list;
+	bool slot_found = false;
 	int ret;
 	int i;

@@ -119,17 +121,20 @@ static int distro_rauc_scan_parts(struct bootflow *bflow)
 		if (desc) {
 			ret = fs_set_blk_dev_with_part(desc, slot->boot_part);
 			if (ret)
-				return log_msg_ret("part", ret);
+				continue;
 			fs_close();
-			ret = fs_set_blk_dev_with_part(desc, slot->root_part);
+			ret = part_get_info(desc, slot->root_part, NULL);
 			if (ret)
-				return log_msg_ret("part", ret);
-			fs_close();
+				continue;
+			slot_found = true;
 		}
 	}
 	str_free_list(boot_order_list);

-	return 0;
+	if (slot_found)
+		return 0;
+
+	return -1;
 }

 static int distro_rauc_read_bootflow(struct udevice *dev, struct bootflow *bflow)
--- a/boot/fdt_support.c
+++ b/boot/fdt_support.c
@@ -27,6 +27,7 @@
 #include <fdtdec.h>
 #include <version.h>
 #include <video.h>
+#include <smbios.h>

 DECLARE_GLOBAL_DATA_PTR;

@@ -333,6 +334,7 @@ int fdt_chosen(void *fdt)
 	int   nodeoffset;
 	int   err;
 	const char *str;		/* used to set string properties */
+	ulong smbiosaddr;		/* SMBIOS table address */

 	err = fdt_check_header(fdt);
 	if (err < 0) {
@@ -387,6 +389,23 @@ int fdt_chosen(void *fdt)
 		return err;
 	}

+	if (CONFIG_IS_ENABLED(GENERATE_SMBIOS_TABLE)) {
+		/* Inject SMBIOS address when we have a valid address.
+		* This is useful for systems using booti/bootm instead of bootefi.
+		* Failure to set this property is non-fatal, we only generate a
+		* warning.
+		*/
+		smbiosaddr = gd_smbios_start();
+		if (smbiosaddr) {
+			err = fdt_setprop_u64(fdt, nodeoffset, "smbios3-entrypoint",
+					smbiosaddr);
+			if (err < 0) {
+				printf("WARNING: could not set smbios3-entrypoint %s.\n",
+				fdt_strerror(err));
+			}
+		}
+	}
+
 	return fdt_fixup_stdout(fdt, nodeoffset);
 }

--- a/cmd/extension_board.c
+++ b/cmd/extension_board.c
@@ -99,6 +99,10 @@ static int do_extension_list(struct cmd_tbl *cmdtp, int flag,
 	int i = 0;

 	extension_list = extension_get_list();
+	if (!extension_list) {
+		printf("No extension device\n");
+		return CMD_RET_FAILURE;
+	}
 	if (!alist_get_ptr(extension_list, 0)) {
 		printf("No extension registered - Please run \"extension scan\"\n");
 		return CMD_RET_SUCCESS;
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -545,7 +545,7 @@ config SPL_SYS_MMCSD_RAW_MODE
 	depends on SPL_DM_MMC || SPL_MMC
 	default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \
 		     ARCH_MX6 || ARCH_MX7 || \
-		     ARCH_ROCKCHIP || ARCH_MVEBU ||  ARCH_SOCFPGA || \
+		     ARCH_ROCKCHIP || ARCH_MVEBU || TARGET_SOCFPGA_GEN5 || \
 		     ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
 		     OMAP54XX || AM33XX || AM43XX || \
 		     TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
@@ -589,7 +589,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
 	default 0x8a if ARCH_MX6 || ARCH_MX7
 	default 0x100 if ARCH_UNIPHIER
 	default 0x0 if ARCH_MVEBU
-	default 0x200 if ARCH_SOCFPGA || ARCH_AT91
+	default 0x200 if TARGET_SOCFPGA_GEN5 || ARCH_AT91
 	default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
 		         OMAP54XX || AM33XX || AM43XX || ARCH_K3
 	default 0x4000 if ARCH_ROCKCHIP
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -3,8 +3,8 @@ CONFIG_SYS_L2CACHE_OFF=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x80110000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SOURCE_FILE="apalis-tk1"
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-apalis"
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -3,8 +3,8 @@ CONFIG_SYS_L2CACHE_OFF=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x80110000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SOURCE_FILE="apalis_t30"
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-apalis"
--- a/configs/brcp150_defconfig
+++ b/configs/brcp150_defconfig
@@ -6,8 +6,8 @@ CONFIG_ARCH_ZYNQ=y
 CONFIG_TEXT_BASE=0x4000000
 CONFIG_SYS_MALLOC_F_LEN=0x1000
 CONFIG_SPL_GPIO=y
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SOURCE_FILE="env/brcp150"
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_SF_DEFAULT_SPEED=100000000
 CONFIG_SF_DEFAULT_MODE=0x3
 CONFIG_ENV_SIZE=0x10000
--- a/configs/brcp170_defconfig
+++ b/configs/brcp170_defconfig
@@ -6,8 +6,8 @@ CONFIG_ARCH_ZYNQ=y
 CONFIG_TEXT_BASE=0x4000000
 CONFIG_SYS_MALLOC_F_LEN=0x1000
 CONFIG_SPL_GPIO=y
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_SF_DEFAULT_SPEED=100000000
 CONFIG_SF_DEFAULT_MODE=0x3
 CONFIG_ENV_SIZE=0x10000
--- a/configs/brcp1_1r_defconfig
+++ b/configs/brcp1_1r_defconfig
@@ -6,8 +6,8 @@ CONFIG_ARCH_ZYNQ=y
 CONFIG_TEXT_BASE=0x4000000
 CONFIG_SYS_MALLOC_F_LEN=0x1000
 CONFIG_SPL_GPIO=y
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_SF_DEFAULT_SPEED=100000000
 CONFIG_SF_DEFAULT_MODE=0x3
 CONFIG_ENV_SIZE=0x10000
--- a/configs/brcp1_1r_switch_defconfig
+++ b/configs/brcp1_1r_switch_defconfig
@@ -6,8 +6,8 @@ CONFIG_ARCH_ZYNQ=y
 CONFIG_TEXT_BASE=0x4000000
 CONFIG_SYS_MALLOC_F_LEN=0x1000
 CONFIG_SPL_GPIO=y
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_SF_DEFAULT_SPEED=100000000
 CONFIG_SF_DEFAULT_MODE=0x3
 CONFIG_ENV_SIZE=0x10000
--- a/configs/brcp1_2r_defconfig
+++ b/configs/brcp1_2r_defconfig
@@ -6,8 +6,8 @@ CONFIG_ARCH_ZYNQ=y
 CONFIG_TEXT_BASE=0x4000000
 CONFIG_SYS_MALLOC_F_LEN=0x1000
 CONFIG_SPL_GPIO=y
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_SF_DEFAULT_SPEED=100000000
 CONFIG_SF_DEFAULT_MODE=0x3
 CONFIG_ENV_SIZE=0x10000
--- a/configs/brsmarc2_defconfig
+++ b/configs/brsmarc2_defconfig
@@ -8,8 +8,8 @@ CONFIG_INITRD_TAG=y
 CONFIG_TEXT_BASE=0x4000000
 CONFIG_SYS_MALLOC_F_LEN=0x1000
 CONFIG_SPL_GPIO=y
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SOURCE_FILE="env/brcp1"
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_SF_DEFAULT_SPEED=100000000
 CONFIG_SF_DEFAULT_MODE=0x3
 CONFIG_ENV_SIZE=0x10000
--- a/configs/cardhu_defconfig
+++ b/configs/cardhu_defconfig
@@ -3,8 +3,8 @@ CONFIG_SYS_HAS_NONCACHED_MEMORY=y
 CONFIG_SYS_L2CACHE_OFF=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x80110000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SOURCE_FILE="cardhu"
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_SF_DEFAULT_SPEED=24000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFE000
--- a/configs/chagall_defconfig
+++ b/configs/chagall_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x80110000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SOURCE_FILE="chagall"
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-pegatron-chagall"
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -22,7 +22,7 @@ CONFIG_BOOTDELAY=1
 CONFIG_OF_ENV_SETUP=y
 CONFIG_BOOTCOMMAND="run ubiboot ; echo ; echo ubiboot failed ; run distro_bootcmd;"
 CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-${fdt_board}.dtb "
+CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri${variant}-${fdt_board}.dtb "
 CONFIG_SYS_PBSIZE=544
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 # CONFIG_DISPLAY_BOARDINFO is not set
--- a/configs/colibri_imx7_emmc_defconfig
+++ b/configs/colibri_imx7_emmc_defconfig
@@ -19,7 +19,7 @@ CONFIG_FIT_VERBOSE=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTDELAY=1
 CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb"
+CONFIG_PREBOOT="test -n ${fdtfile} || setenv fdtfile ${soc}-colibri${variant}-${fdt_board}.dtb"
 CONFIG_SYS_PBSIZE=544
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 # CONFIG_DISPLAY_BOARDINFO is not set
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -3,8 +3,8 @@ CONFIG_SYS_L2CACHE_OFF=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x00110000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SOURCE_FILE="colibri_t20"
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0x200000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-colibri"
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -3,8 +3,8 @@ CONFIG_SYS_L2CACHE_OFF=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x80110000
 CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SOURCE_FILE="colibri_t30"
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-colibri"
--- a/configs/endeavoru_defconfig
+++ b/configs/endeavoru_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x80110000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SOURCE_FILE="endeavoru"
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-htc-endeavoru"
--- a/configs/exynos-mobile_defconfig
+++ b/configs/exynos-mobile_defconfig
@@ -0,0 +1,70 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=26000000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_EXYNOS=y
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x16000
+CONFIG_TARGET_EXYNOS_MOBILE=y
+CONFIG_NR_DRAM_BANKS=3
+CONFIG_DEFAULT_DEVICE_TREE="exynos/exynos7870-a2corelte"
+CONFIG_SYS_BOOTM_LEN=0x2000000
+CONFIG_SYS_LOAD_ADDR=0x80000000
+CONFIG_ARMV8_CNTFRQ_BROKEN=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_BUTTON_CMD=y
+CONFIG_SAVE_PREV_BL_FDT_ADDR=y
+CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
+CONFIG_SYS_PBSIZE=1024
+CONFIG_BOARD_TYPES=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_MISC_INIT_R=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_EFI_PARTITION=y
+CONFIG_OF_UPSTREAM=y
+CONFIG_OF_LIST="exynos/exynos7870-a2corelte exynos/exynos7870-j6lte exynos/exynos7870-on7xelte"
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_REMAP_PHONE_KEYS=y
+CONFIG_CLK_EXYNOS7870=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0xdead0000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_SYS_I2C_S3C24X0=y
+CONFIG_BUTTON_KEYBOARD=y
+CONFIG_MISC=y
+CONFIG_MMC_BROKEN_CD=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_DW=y
+CONFIG_PHY=y
+CONFIG_PHY_EXYNOS_USBDRD=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_EXYNOS78x0=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_S2MPS11=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_S2MPS11=y
+CONFIG_SOC_SAMSUNG=y
+CONFIG_EXYNOS_PMU=y
+CONFIG_SYSRESET=y
+CONFIG_SYSRESET_CMD_POWEROFF=y
+CONFIG_SYSRESET_SYSCON=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Samsung"
+CONFIG_USB_GADGET_VENDOR_NUM=0x04e8
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6602
+CONFIG_VIDEO=y
+CONFIG_VIDEO_SIMPLE=y
+CONFIG_FS_EXT4=y
+CONFIG_FS_FAT=y
--- a/configs/grouper_defconfig
+++ b/configs/grouper_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x80110000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SOURCE_FILE="grouper"
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-asus-nexus7-grouper-E1565"
--- a/configs/ideapad-yoga-11_defconfig
+++ b/configs/ideapad-yoga-11_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x80110000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SOURCE_FILE="ideapad-yoga-11"
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-lenovo-ideapad-yoga-11"
--- a/configs/imx6dl_sielaff_defconfig
+++ b/configs/imx6dl_sielaff_defconfig
@@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SOURCE_FILE="imx6dl-sielaff"
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_ENV_SIZE=0x10000
 CONFIG_ENV_OFFSET=0xF0000
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SOURCE_FILE="imx8mn_beacon"
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SOURCE_FILE="imx8mn_beacon"
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
--- a/configs/imx8mn_beacon_fspi_defconfig
+++ b/configs/imx8mn_beacon_fspi_defconfig
@@ -5,8 +5,8 @@ CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SOURCE_FILE="imx8mn_beacon"
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
--- a/configs/imx943_evk_defconfig
+++ b/configs/imx943_evk_defconfig
@@ -6,8 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x10000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SOURCE_FILE="imx94_evk"
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x700000
 CONFIG_DM_GPIO=y
--- a/configs/imx95_15x15_evk_defconfig
+++ b/configs/imx95_15x15_evk_defconfig
@@ -6,8 +6,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x10000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=3
 CONFIG_ENV_SOURCE_FILE="imx95_evk"
+CONFIG_NR_DRAM_BANKS=3
 CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x700000
--- a/configs/imxrt1050-evk_fspi_defconfig
+++ b/configs/imxrt1050-evk_fspi_defconfig
@@ -8,8 +8,8 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SOURCE_FILE="imxrt1050-evk-nor"
+CONFIG_NR_DRAM_BANKS=1
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20020000
 CONFIG_ENV_OFFSET=0x80000
--- a/configs/mocha_defconfig
+++ b/configs/mocha_defconfig
@@ -2,8 +2,8 @@ CONFIG_ARM=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x80110000
 CONFIG_SYS_MALLOC_LEN=0x2500000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SOURCE_FILE="mocha"
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra124-xiaomi-mocha"
--- a/configs/mot_defconfig
+++ b/configs/mot_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x00110000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SOURCE_FILE="mot"
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-motorola-olympus"
--- a/configs/n1_defconfig
+++ b/configs/n1_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x00110000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SOURCE_FILE="n1"
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra20-samsung-n1"
--- a/configs/ouya_defconfig
+++ b/configs/ouya_defconfig
@@ -1,8 +1,8 @@
 CONFIG_ARM=y
 CONFIG_ARCH_TEGRA=y
 CONFIG_TEXT_BASE=0x80110000
-CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SOURCE_FILE="ouya"
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0xFFFFD000
 CONFIG_DEFAULT_DEVICE_TREE="tegra30-ouya"
--- a/Show More
+++ b/Show More