clk: rockchip: Add support for RK3528
Add clock driver for RK3528. Imported from vendor U-Boot linux-6.1-stan-rkr5 tag with minor adjustments and fixes for mainline. Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Joseph Chen
@@ -15,6 +15,13 @@ struct udevice;
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#define RKCLK_PLL_MODE_NORMAL 1
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#define RKCLK_PLL_MODE_DEEP 2
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/*
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* PLL flags
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*/
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#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
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/* normal mode only. now only for pll_rk3036, pll_rk3328 type */
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#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
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enum {
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ROCKCHIP_SYSCON_NOC,
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ROCKCHIP_SYSCON_GRF,
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@@ -207,6 +214,16 @@ int rockchip_reset_bind(struct udevice *pdev, u32 reg_offset, u32 reg_number);
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*/
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int rockchip_reset_bind_lut(struct udevice *pdev, const int *lookup_table,
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u32 reg_offset, u32 reg_number);
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/*
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* rk3528_reset_bind_lut() - Bind soft reset device as child of clock device
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* using dedicated RK3528 lookup table
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*
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* @pdev: clock udevice
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* @reg_offset: the first offset in cru for softreset registers
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* @reg_number: the reg numbers of softreset registers
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* Return: 0 success, or error value
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*/
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int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number);
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/*
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* rk3588_reset_bind_lut() - Bind soft reset device as child of clock device
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* using dedicated RK3588 lookup table
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388
arch/arm/include/asm/arch-rockchip/cru_rk3528.h
Normal file
388
arch/arm/include/asm/arch-rockchip/cru_rk3528.h
Normal file
@@ -0,0 +1,388 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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* Author: Joseph Chen <chenjh@rock-chips.com>
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*/
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#ifndef _ASM_ARCH_CRU_RK3528_H
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#define _ASM_ARCH_CRU_RK3528_H
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#define MHz 1000000
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#define KHz 1000
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#define OSC_HZ (24 * MHz)
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#define CPU_PVTPLL_HZ (1200 * MHz)
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#define APLL_HZ (600 * MHz)
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#define GPLL_HZ (1188 * MHz)
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#define CPLL_HZ (996 * MHz)
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#define PPLL_HZ (1000 * MHz)
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/* RK3528 pll id */
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enum rk3528_pll_id {
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APLL,
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CPLL,
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GPLL,
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PPLL,
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DPLL,
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PLL_COUNT,
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};
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struct rk3528_clk_priv {
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struct rk3528_cru *cru;
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unsigned long ppll_hz;
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unsigned long gpll_hz;
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unsigned long cpll_hz;
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unsigned long armclk_hz;
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unsigned long armclk_enter_hz;
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unsigned long armclk_init_hz;
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bool sync_kernel;
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};
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struct rk3528_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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unsigned int con4;
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unsigned int reserved0[3];
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};
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#define RK3528_CRU_BASE ((struct rk3528_cru *)0xff4a0000)
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struct rk3528_cru {
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unsigned int apll_con[5];
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unsigned int reserved0014[3];
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unsigned int cpll_con[5];
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unsigned int reserved0034[11];
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unsigned int gpll_con[5];
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unsigned int reserved0074[51 + 32];
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unsigned int reserved01c0[48];
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unsigned int mode_con[1];
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unsigned int reserved0284[31];
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unsigned int clksel_con[91];
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unsigned int reserved046c[229];
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unsigned int gate_con[46];
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unsigned int reserved08b8[82];
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unsigned int softrst_con[47];
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unsigned int reserved0abc[81];
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unsigned int glb_cnt_th;
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unsigned int glb_rst_st;
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unsigned int glb_srst_fst;
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unsigned int glb_srst_snd;
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unsigned int glb_rst_con;
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unsigned int reserved0c14[6];
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unsigned int corewfi_con;
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unsigned int reserved0c30[15604];
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/* pmucru */
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unsigned int reserved10000[192];
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unsigned int pmuclksel_con[3];
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unsigned int reserved1030c[317];
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unsigned int pmugate_con[3];
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unsigned int reserved1080c[125];
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unsigned int pmusoftrst_con[3];
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unsigned int reserved10a08[7550 + 8191];
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/* pciecru */
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unsigned int reserved20000[32];
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unsigned int ppll_con[5];
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unsigned int reserved20094[155];
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unsigned int pcieclksel_con[2];
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unsigned int reserved20308[318];
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unsigned int pciegate_con;
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};
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check_member(rk3528_cru, pciegate_con, 0x20800);
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struct pll_rate_table {
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unsigned long rate;
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unsigned int fbdiv;
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unsigned int postdiv1;
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unsigned int refdiv;
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unsigned int postdiv2;
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unsigned int dsmpd;
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unsigned int frac;
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};
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#define RK3528_PMU_CRU_BASE 0x10000
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#define RK3528_PCIE_CRU_BASE 0x20000
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#define RK3528_DDRPHY_CRU_BASE 0x28000
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#define RK3528_PLL_CON(x) ((x) * 0x4)
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#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
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#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
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#define RK3528_MODE_CON 0x280
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#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
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#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
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#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
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#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
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#define RK3528_DIV_ACLK_M_CORE_SHIFT 11
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#define RK3528_DIV_ACLK_M_CORE_MASK (0x1f << RK3528_DIV_ACLK_M_CORE_SHIFT)
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#define RK3528_DIV_PCLK_DBG_SHIFT 1
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#define RK3528_DIV_PCLK_DBG_MASK (0x1f << RK3528_DIV_PCLK_DBG_SHIFT)
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enum {
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/* CRU_CLKSEL_CON00 */
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CLK_MATRIX_50M_SRC_DIV_SHIFT = 2,
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CLK_MATRIX_50M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_50M_SRC_DIV_SHIFT,
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CLK_MATRIX_100M_SRC_DIV_SHIFT = 7,
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CLK_MATRIX_100M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_100M_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON01 */
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CLK_MATRIX_150M_SRC_DIV_SHIFT = 0,
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CLK_MATRIX_150M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_150M_SRC_DIV_SHIFT,
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CLK_MATRIX_200M_SRC_DIV_SHIFT = 5,
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CLK_MATRIX_200M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_200M_SRC_DIV_SHIFT,
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CLK_MATRIX_250M_SRC_DIV_SHIFT = 10,
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CLK_MATRIX_250M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_250M_SRC_DIV_SHIFT,
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CLK_MATRIX_250M_SRC_SEL_SHIFT = 15,
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CLK_MATRIX_250M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_250M_SRC_SEL_SHIFT,
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/* CRU_CLKSEL_CON02 */
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CLK_MATRIX_300M_SRC_DIV_SHIFT = 0,
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CLK_MATRIX_300M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_300M_SRC_DIV_SHIFT,
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CLK_MATRIX_339M_SRC_DIV_SHIFT = 5,
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CLK_MATRIX_339M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_339M_SRC_DIV_SHIFT,
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CLK_MATRIX_400M_SRC_DIV_SHIFT = 10,
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CLK_MATRIX_400M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_400M_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON03 */
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CLK_MATRIX_500M_SRC_DIV_SHIFT = 6,
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CLK_MATRIX_500M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_500M_SRC_DIV_SHIFT,
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CLK_MATRIX_500M_SRC_SEL_SHIFT = 11,
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CLK_MATRIX_500M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_500M_SRC_SEL_SHIFT,
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/* CRU_CLKSEL_CON04 */
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CLK_MATRIX_600M_SRC_DIV_SHIFT = 0,
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CLK_MATRIX_600M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_600M_SRC_DIV_SHIFT,
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CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX = 0U,
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CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX = 1U,
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CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX = 0U,
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CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX = 1U,
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/* PMUCRU_CLKSEL_CON00 */
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CLK_I2C2_SEL_SHIFT = 0,
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CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT,
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/* PCIE_CRU_CLKSEL_CON01 */
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PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT = 7,
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PCIE_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT,
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PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT = 11,
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PCIE_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON32 */
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DCLK_VOP_SRC0_SEL_SHIFT = 10,
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DCLK_VOP_SRC0_SEL_MASK = 0x1 << DCLK_VOP_SRC0_SEL_SHIFT,
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DCLK_VOP_SRC0_DIV_SHIFT = 2,
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DCLK_VOP_SRC0_DIV_MASK = 0xFF << DCLK_VOP_SRC0_DIV_SHIFT,
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/* CRU_CLKSEL_CON33 */
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DCLK_VOP_SRC1_SEL_SHIFT = 8,
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DCLK_VOP_SRC1_SEL_MASK = 0x1 << DCLK_VOP_SRC1_SEL_SHIFT,
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DCLK_VOP_SRC1_DIV_SHIFT = 0,
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DCLK_VOP_SRC1_DIV_MASK = 0xFF << DCLK_VOP_SRC1_DIV_SHIFT,
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/* CRU_CLKSEL_CON43 */
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CLK_CORE_CRYPTO_SEL_SHIFT = 14,
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CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT,
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ACLK_BUS_VOPGL_ROOT_DIV_SHIFT = 0U,
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ACLK_BUS_VOPGL_ROOT_DIV_MASK = 0x7U << ACLK_BUS_VOPGL_ROOT_DIV_SHIFT,
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/* CRU_CLKSEL_CON44 */
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CLK_PWM0_SEL_SHIFT = 6,
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CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT,
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CLK_PWM1_SEL_SHIFT = 8,
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CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
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CLK_PWM0_SEL_CLK_MATRIX_100M_SRC = 0U,
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CLK_PWM0_SEL_CLK_MATRIX_50M_SRC = 1U,
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CLK_PWM0_SEL_XIN_OSC0_FUNC = 2U,
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CLK_PWM1_SEL_CLK_MATRIX_100M_SRC = 0U,
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CLK_PWM1_SEL_CLK_MATRIX_50M_SRC = 1U,
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CLK_PWM1_SEL_XIN_OSC0_FUNC = 2U,
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CLK_PKA_CRYPTO_SEL_SHIFT = 0,
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CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT,
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CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
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CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
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CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
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CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
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CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
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CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
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CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
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CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
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/* CRU_CLKSEL_CON60 */
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CLK_MATRIX_25M_SRC_DIV_SHIFT = 2,
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CLK_MATRIX_25M_SRC_DIV_MASK = 0xff << CLK_MATRIX_25M_SRC_DIV_SHIFT,
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CLK_MATRIX_125M_SRC_DIV_SHIFT = 10,
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CLK_MATRIX_125M_SRC_DIV_MASK = 0x1f << CLK_MATRIX_125M_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON61 */
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SCLK_SFC_DIV_SHIFT = 6,
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SCLK_SFC_DIV_MASK = 0x3F << SCLK_SFC_DIV_SHIFT,
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SCLK_SFC_SEL_SHIFT = 12,
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SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT,
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SCLK_SFC_SEL_CLK_GPLL_MUX = 0U,
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SCLK_SFC_SEL_CLK_CPLL_MUX = 1U,
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SCLK_SFC_SEL_XIN_OSC0_FUNC = 2U,
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/* CRU_CLKSEL_CON62 */
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CCLK_SRC_EMMC_DIV_SHIFT = 0,
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CCLK_SRC_EMMC_DIV_MASK = 0x3F << CCLK_SRC_EMMC_DIV_SHIFT,
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CCLK_SRC_EMMC_SEL_SHIFT = 6,
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CCLK_SRC_EMMC_SEL_MASK = 0x3 << CCLK_SRC_EMMC_SEL_SHIFT,
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BCLK_EMMC_SEL_SHIFT = 8,
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BCLK_EMMC_SEL_MASK = 0x3 << BCLK_EMMC_SEL_SHIFT,
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/* CRU_CLKSEL_CON63 */
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CLK_I2C3_SEL_SHIFT = 12,
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CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT,
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CLK_I2C5_SEL_SHIFT = 14,
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CLK_I2C5_SEL_MASK = 0x3 << CLK_I2C5_SEL_SHIFT,
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CLK_SPI1_SEL_SHIFT = 10,
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CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT,
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/* CRU_CLKSEL_CON64 */
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CLK_I2C6_SEL_SHIFT = 0,
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CLK_I2C6_SEL_MASK = 0x3 << CLK_I2C6_SEL_SHIFT,
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/* CRU_CLKSEL_CON74 */
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CLK_SARADC_DIV_SHIFT = 0,
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CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT,
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CLK_TSADC_DIV_SHIFT = 3,
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CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT,
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CLK_TSADC_TSEN_DIV_SHIFT = 8,
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CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT,
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/* CRU_CLKSEL_CON79 */
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CLK_I2C1_SEL_SHIFT = 9,
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CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT,
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CLK_I2C0_SEL_SHIFT = 11,
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CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT,
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CLK_SPI0_SEL_SHIFT = 13,
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CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT,
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/* CRU_CLKSEL_CON83 */
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ACLK_VOP_ROOT_DIV_SHIFT = 12,
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ACLK_VOP_ROOT_DIV_MASK = 0x7 << ACLK_VOP_ROOT_DIV_SHIFT,
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ACLK_VOP_ROOT_SEL_SHIFT = 15,
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ACLK_VOP_ROOT_SEL_MASK = 0x1 << ACLK_VOP_ROOT_SEL_SHIFT,
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/* CRU_CLKSEL_CON84 */
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DCLK_VOP0_SEL_SHIFT = 0,
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DCLK_VOP0_SEL_MASK = 0x1 << DCLK_VOP0_SEL_SHIFT,
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DCLK_VOP_SRC_SEL_CLK_GPLL_MUX = 0U,
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DCLK_VOP_SRC_SEL_CLK_CPLL_MUX = 1U,
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ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX = 0U,
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ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX = 1U,
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DCLK_VOP0_SEL_DCLK_VOP_SRC0 = 0U,
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DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO = 1U,
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/* CRU_CLKSEL_CON85 */
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CLK_I2C4_SEL_SHIFT = 13,
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CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT,
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CLK_I2C7_SEL_SHIFT = 0,
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CLK_I2C7_SEL_MASK = 0x3 << CLK_I2C7_SEL_SHIFT,
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CLK_I2C3_SEL_CLK_MATRIX_200M_SRC = 0U,
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CLK_I2C3_SEL_CLK_MATRIX_100M_SRC = 1U,
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CLK_I2C3_SEL_CLK_MATRIX_50M_SRC = 2U,
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CLK_I2C3_SEL_XIN_OSC0_FUNC = 3U,
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CLK_SPI1_SEL_CLK_MATRIX_200M_SRC = 0U,
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CLK_SPI1_SEL_CLK_MATRIX_100M_SRC = 1U,
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CLK_SPI1_SEL_CLK_MATRIX_50M_SRC = 2U,
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CLK_SPI1_SEL_XIN_OSC0_FUNC = 3U,
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CCLK_SRC_SDMMC0_DIV_SHIFT = 0,
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CCLK_SRC_SDMMC0_DIV_MASK = 0x3F << CCLK_SRC_SDMMC0_DIV_SHIFT,
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CCLK_SRC_SDMMC0_SEL_SHIFT = 6,
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CCLK_SRC_SDMMC0_SEL_MASK = 0x3 << CCLK_SRC_SDMMC0_SEL_SHIFT,
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CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX = 0U,
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CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX = 1U,
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CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC = 2U,
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BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC = 0U,
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BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC = 1U,
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BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC = 2U,
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BCLK_EMMC_SEL_XIN_OSC0_FUNC = 3U,
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CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX = 0U,
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CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX = 1U,
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CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC = 2U,
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/* CRU_CLKSEL_CON04 */
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CLK_UART0_SRC_DIV_SHIFT = 5,
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||||
CLK_UART0_SRC_DIV_MASK = 0x1F << CLK_UART0_SRC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON05 */
|
||||
CLK_UART0_FRAC_DIV_SHIFT = 0,
|
||||
CLK_UART0_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART0_FRAC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON06 */
|
||||
SCLK_UART0_SRC_SEL_SHIFT = 0,
|
||||
SCLK_UART0_SRC_SEL_MASK = 0x3 << SCLK_UART0_SRC_SEL_SHIFT,
|
||||
CLK_UART1_SRC_DIV_SHIFT = 2,
|
||||
CLK_UART1_SRC_DIV_MASK = 0x1F << CLK_UART1_SRC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON07 */
|
||||
CLK_UART1_FRAC_DIV_SHIFT = 0,
|
||||
CLK_UART1_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART1_FRAC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON08 */
|
||||
SCLK_UART1_SRC_SEL_SHIFT = 0,
|
||||
SCLK_UART1_SRC_SEL_MASK = 0x3 << SCLK_UART1_SRC_SEL_SHIFT,
|
||||
CLK_UART2_SRC_DIV_SHIFT = 2,
|
||||
CLK_UART2_SRC_DIV_MASK = 0x1F << CLK_UART2_SRC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON09 */
|
||||
CLK_UART2_FRAC_DIV_SHIFT = 0,
|
||||
CLK_UART2_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART2_FRAC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON10 */
|
||||
SCLK_UART2_SRC_SEL_SHIFT = 0,
|
||||
SCLK_UART2_SRC_SEL_MASK = 0x3 << SCLK_UART2_SRC_SEL_SHIFT,
|
||||
CLK_UART3_SRC_DIV_SHIFT = 2,
|
||||
CLK_UART3_SRC_DIV_MASK = 0x1F << CLK_UART3_SRC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON11 */
|
||||
CLK_UART3_FRAC_DIV_SHIFT = 0,
|
||||
CLK_UART3_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART3_FRAC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON12 */
|
||||
SCLK_UART3_SRC_SEL_SHIFT = 0,
|
||||
SCLK_UART3_SRC_SEL_MASK = 0x3 << SCLK_UART3_SRC_SEL_SHIFT,
|
||||
CLK_UART4_SRC_DIV_SHIFT = 2,
|
||||
CLK_UART4_SRC_DIV_MASK = 0x1F << CLK_UART4_SRC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON13 */
|
||||
CLK_UART4_FRAC_DIV_SHIFT = 0,
|
||||
CLK_UART4_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART4_FRAC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON14 */
|
||||
SCLK_UART4_SRC_SEL_SHIFT = 0,
|
||||
SCLK_UART4_SRC_SEL_MASK = 0x3 << SCLK_UART4_SRC_SEL_SHIFT,
|
||||
CLK_UART5_SRC_DIV_SHIFT = 2,
|
||||
CLK_UART5_SRC_DIV_MASK = 0x1F << CLK_UART5_SRC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON15 */
|
||||
CLK_UART5_FRAC_DIV_SHIFT = 0,
|
||||
CLK_UART5_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART5_FRAC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON16 */
|
||||
SCLK_UART5_SRC_SEL_SHIFT = 0,
|
||||
SCLK_UART5_SRC_SEL_MASK = 0x3 << SCLK_UART5_SRC_SEL_SHIFT,
|
||||
CLK_UART6_SRC_DIV_SHIFT = 2,
|
||||
CLK_UART6_SRC_DIV_MASK = 0x1F << CLK_UART6_SRC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON17 */
|
||||
CLK_UART6_FRAC_DIV_SHIFT = 0,
|
||||
CLK_UART6_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART6_FRAC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON18 */
|
||||
SCLK_UART6_SRC_SEL_SHIFT = 0,
|
||||
SCLK_UART6_SRC_SEL_MASK = 0x3 << SCLK_UART6_SRC_SEL_SHIFT,
|
||||
CLK_UART7_SRC_DIV_SHIFT = 2,
|
||||
CLK_UART7_SRC_DIV_MASK = 0x1F << CLK_UART7_SRC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON19 */
|
||||
CLK_UART7_FRAC_DIV_SHIFT = 0,
|
||||
CLK_UART7_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART7_FRAC_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON20 */
|
||||
SCLK_UART7_SRC_SEL_SHIFT = 0,
|
||||
SCLK_UART7_SRC_SEL_MASK = 0x3 << SCLK_UART7_SRC_SEL_SHIFT,
|
||||
SCLK_UART0_SRC_SEL_CLK_UART0_SRC = 0U,
|
||||
SCLK_UART0_SRC_SEL_CLK_UART0_FRAC = 1U,
|
||||
SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC = 2U,
|
||||
|
||||
/* CRU_CLKSEL_CON60 */
|
||||
CLK_GMAC1_VPU_25M_DIV_SHIFT = 2,
|
||||
CLK_GMAC1_VPU_25M_DIV_MASK = 0xFF << CLK_GMAC1_VPU_25M_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON66 */
|
||||
CLK_GMAC1_SRC_VPU_DIV_SHIFT = 0,
|
||||
CLK_GMAC1_SRC_VPU_DIV_MASK = 0x3F << CLK_GMAC1_SRC_VPU_DIV_SHIFT,
|
||||
/* CRU_CLKSEL_CON84 */
|
||||
CLK_GMAC0_SRC_DIV_SHIFT = 3,
|
||||
CLK_GMAC0_SRC_DIV_MASK = 0x3F << CLK_GMAC0_SRC_DIV_SHIFT,
|
||||
};
|
||||
|
||||
#endif /* _ASM_ARCH_CRU_RK3528_H */
|
||||
@@ -15,6 +15,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3528) += clk_rk3528.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
|
||||
obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o
|
||||
obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o
|
||||
|
||||
@@ -309,9 +309,11 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
|
||||
* When power on or changing PLL setting,
|
||||
* we must force PLL into slow mode to ensure output stable clock.
|
||||
*/
|
||||
rk_clrsetreg(base + pll->mode_offset,
|
||||
pll->mode_mask << pll->mode_shift,
|
||||
RKCLK_PLL_MODE_SLOW << pll->mode_shift);
|
||||
if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
|
||||
rk_clrsetreg(base + pll->mode_offset,
|
||||
pll->mode_mask << pll->mode_shift,
|
||||
RKCLK_PLL_MODE_SLOW << pll->mode_shift);
|
||||
}
|
||||
|
||||
/* Power down */
|
||||
rk_setreg(base + pll->con_offset + 0x4,
|
||||
@@ -345,8 +347,11 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll,
|
||||
while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))
|
||||
udelay(1);
|
||||
|
||||
rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
|
||||
RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
|
||||
if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
|
||||
rk_clrsetreg(base + pll->mode_offset,
|
||||
pll->mode_mask << pll->mode_shift,
|
||||
RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
|
||||
}
|
||||
debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
|
||||
pll, readl(base + pll->con_offset),
|
||||
readl(base + pll->con_offset + 0x4),
|
||||
@@ -362,12 +367,18 @@ static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll,
|
||||
u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac;
|
||||
u32 con = 0, shift, mask;
|
||||
ulong rate;
|
||||
int mode;
|
||||
|
||||
con = readl(base + pll->mode_offset);
|
||||
shift = pll->mode_shift;
|
||||
mask = pll->mode_mask << shift;
|
||||
|
||||
switch ((con & mask) >> shift) {
|
||||
if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE))
|
||||
mode = (con & mask) >> shift;
|
||||
else
|
||||
mode = RKCLK_PLL_MODE_NORMAL;
|
||||
|
||||
switch (mode) {
|
||||
case RKCLK_PLL_MODE_SLOW:
|
||||
return OSC_HZ;
|
||||
case RKCLK_PLL_MODE_NORMAL:
|
||||
|
||||
1754
drivers/clk/rockchip/clk_rk3528.c
Normal file
1754
drivers/clk/rockchip/clk_rk3528.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -17,7 +17,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
|
||||
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
|
||||
obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o
|
||||
obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o
|
||||
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3588.o
|
||||
obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o rst-rk3528.o rst-rk3588.o
|
||||
obj-$(CONFIG_RESET_MESON) += reset-meson.o
|
||||
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
|
||||
obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
|
||||
|
||||
302
drivers/reset/rst-rk3528.c
Normal file
302
drivers/reset/rst-rk3528.c
Normal file
@@ -0,0 +1,302 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
|
||||
* Based on Sebastian Reichel's implementation for RK3588
|
||||
*/
|
||||
|
||||
#include <dm.h>
|
||||
#include <asm/arch-rockchip/clock.h>
|
||||
#include <dt-bindings/reset/rockchip,rk3528-cru.h>
|
||||
|
||||
/* 0xFF4A0000 + 0x0A00 */
|
||||
#define RK3528_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
|
||||
|
||||
/* mapping table for reset ID to register offset */
|
||||
static const int rk3528_register_offset[] = {
|
||||
/* CRU_SOFTRST_CON03 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE0_PO, 3, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE1_PO, 3, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE2_PO, 3, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE3_PO, 3, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE0, 3, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE1, 3, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE2, 3, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE3, 3, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_NL2, 3, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE_BIU, 3, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE_CRYPTO, 3, 10),
|
||||
|
||||
/* CRU_SOFTRST_CON05 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DBG, 5, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_POT_DBG, 5, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_NT_DBG, 5, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON06 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 6, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DAPLITE_BIU, 6, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CPU_BIU, 6, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 6, 7),
|
||||
|
||||
/* CRU_SOFTRST_CON08 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_BUS_VOPGL_BIU, 8, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_BUS_H_BIU, 8, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 8, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 8, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 8, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 8, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DFT2APB, 8, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 8, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON09 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_BUS_M_BIU, 9, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_GIC, 9, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 9, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_DMAC, 9, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_TIMER, 9, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TIMER0, 9, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TIMER1, 9, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TIMER2, 9, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TIMER3, 9, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TIMER4, 9, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TIMER5, 9, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_JDBCK_DAP, 9, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_JDBCK_DAP, 9, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_WDT_NS, 9, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON10 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_T_WDT_NS, 10, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_TRNG_NS, 10, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART0, 10, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART0, 10, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_PKA_CRYPTO, 10, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_CRYPTO, 10, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_CRYPTO, 10, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 10, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 10, 14),
|
||||
|
||||
/* CRU_SOFTRST_CON11 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_PWM0, 11, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_PWM0, 11, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_PWM1, 11, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_PWM1, 11, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_SCR, 11, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_DCF, 11, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_INTMUX, 11, 12),
|
||||
|
||||
/* CRU_SOFTRST_CON25 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VPU_BIU, 25, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 25, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_VPU_BIU, 25, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VPU, 25, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_VPU, 25, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CRU_PCIE, 25, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_VPU_GRF, 25, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SFC, 25, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_SFC, 25, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_C_EMMC, 25, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON26 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_EMMC, 26, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_EMMC, 26, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_B_EMMC, 26, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_T_EMMC, 26, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_GPIO1, 26, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO1, 26, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VPU_L_BIU, 26, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_VPU_IOC, 26, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S0, 26, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S0, 26, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S2, 26, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S2, 26, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_ACODEC, 26, 13),
|
||||
|
||||
/* CRU_SOFTRST_CON27 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_GPIO3, 27, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO3, 27, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_SPI1, 27, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_SPI1, 27, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART2, 27, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART2, 27, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART5, 27, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART5, 27, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART6, 27, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART6, 27, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART7, 27, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART7, 27, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_I2C3, 27, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON28 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_I2C3, 28, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_I2C5, 28, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_I2C5, 28, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_I2C6, 28, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_I2C6, 28, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_MAC, 28, 5),
|
||||
|
||||
/* CRU_SOFTRST_CON30 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_PCIE, 30, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_PCIE_PIPE_PHY, 30, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_PCIE_POWER_UP, 30, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_PCIE_PHY, 30, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_PIPE_GRF, 30, 7),
|
||||
|
||||
/* CRU_SOFTRST_CON32 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SDIO0, 32, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SDIO1, 32, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TS_0, 32, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TS_1, 32, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CAN2, 32, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CAN2, 32, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CAN3, 32, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CAN3, 32, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_SARADC, 32, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_SARADC, 32, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_SARADC_PHY, 32, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_TSADC, 32, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TSADC, 32, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON33 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_USB3OTG, 33, 1),
|
||||
|
||||
/* CRU_SOFTRST_CON34 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_GPU_BIU, 34, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 34, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_GPU, 34, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_GPU, 34, 9),
|
||||
|
||||
/* CRU_SOFTRST_CON36 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC_BIU, 36, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC_BIU, 36, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_BIU, 36, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_RKVENC, 36, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_RKVENC, 36, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE_RKVENC, 36, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S1, 36, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S1, 36, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_I2C1, 36, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_I2C1, 36, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_I2C0, 36, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_I2C0, 36, 14),
|
||||
|
||||
/* CRU_SOFTRST_CON37 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_SPI0, 37, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_SPI0, 37, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_GPIO4, 37, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO4, 37, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_IOC, 37, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SPDIF, 37, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_M_SPDIF, 37, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON38 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_PDM, 38, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_M_PDM, 38, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART1, 38, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART1, 38, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART3, 38, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART3, 38, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_RKVENC_GRF, 38, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CAN0, 38, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CAN0, 38, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CAN1, 38, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CAN1, 38, 10),
|
||||
|
||||
/* CRU_SOFTRST_CON39 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VO_BIU, 39, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_VO_BIU, 39, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_VO_BIU, 39, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_RGA2E, 39, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_RGA2E, 39, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE_RGA2E, 39, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_VDPP, 39, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VDPP, 39, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_CORE_VDPP, 39, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_VO_GRF, 39, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_CRU, 39, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON40 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 40, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_VOP, 40, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_D_VOP0, 40, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_D_VOP1, 40, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VOP, 40, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_HDMI, 40, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_HDMI, 40, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_HDMIPHY, 40, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_HDCP_KEY, 40, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON41 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_HDCP, 41, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_HDCP, 41, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_HDCP, 41, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_CVBS, 41, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_D_CVBS_VOP, 41, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_D_4X_CVBS_VOP, 41, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 41, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 41, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_VO_L_BIU, 41, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_MAC_VO, 41, 10),
|
||||
|
||||
/* CRU_SOFTRST_CON42 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 42, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SAI_I2S3, 42, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_M_SAI_I2S3, 42, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_MACPHY, 42, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_VCDCPHY, 42, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_GPIO2, 42, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_DB_GPIO2, 42, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_VO_IOC, 42, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_SDMMC0, 42, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 42, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 42, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 42, 13),
|
||||
|
||||
/* CRU_SOFTRST_CON43 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_HDMIHDP0, 43, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST, 43, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_USBHOST_ARB, 43, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_HOST_UTMI, 43, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_UART4, 43, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_S_UART4, 43, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_I2C4, 43, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_I2C4, 43, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_I2C7, 43, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_I2C7, 43, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_USBPHY, 43, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_USBPHY_POR, 43, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_USBPHY_OTG, 43, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON44 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_USBPHY_HOST, 44, 0),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY_CRU, 44, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 44, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 44, 7),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_RKVDEC, 44, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_H_RKVDEC, 44, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 44, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_REF_PVTPLL_RKVDEC, 44, 12),
|
||||
|
||||
/* CRU_SOFTRST_CON45 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 45, 1),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DDRC, 45, 2),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DDRMON, 45, 3),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_TIMER_DDRMON, 45, 4),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_MSCH_BIU, 45, 5),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 45, 6),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DDR_HWLP, 45, 8),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_P_DDRPHY, 45, 9),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_MSCH_BIU, 45, 10),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL, 45, 11),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_DDR_UPCTL, 45, 12),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_DDRMON, 45, 13),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_DDR_SCRAMBLE, 45, 14),
|
||||
RK3528_CRU_RESET_OFFSET(SRST_A_SPLIT, 45, 15),
|
||||
|
||||
/* CRU_SOFTRST_CON46 */
|
||||
RK3528_CRU_RESET_OFFSET(SRST_DDR_PHY, 46, 0),
|
||||
};
|
||||
|
||||
int rk3528_reset_bind_lut(struct udevice *pdev, u32 reg_offset, u32 reg_number)
|
||||
{
|
||||
return rockchip_reset_bind_lut(pdev, rk3528_register_offset,
|
||||
reg_offset, reg_number);
|
||||
}
|
||||
Reference in New Issue
Block a user