Merge tag 'u-boot-ufs-next-20250318' of https://source.denx.de/u-boot/custodians/u-boot-ufs into next
- initial cleanup and defines sync with Linux v6.12
This commit is contained in:
Tom Rini
@@ -19,6 +19,7 @@
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#include <malloc.h>
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#include <hexdump.h>
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#include <scsi.h>
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#include <ufs.h>
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#include <asm/io.h>
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#include <asm/dma-mapping.h>
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#include <linux/bitops.h>
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@@ -313,16 +314,12 @@ static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
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ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
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&tx_lanes);
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for (i = 0; i < tx_lanes; i++) {
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unsigned int val = UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
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UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i));
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if (!peer)
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err = ufshcd_dme_set(hba,
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UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
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UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
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0);
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err = ufshcd_dme_set(hba, val, 0);
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else
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err = ufshcd_dme_peer_set(hba,
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UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
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UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
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0);
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err = ufshcd_dme_peer_set(hba, val, 0);
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if (err) {
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dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d\n",
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__func__, peer, i, err);
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@@ -1034,8 +1031,8 @@ static inline void ufshcd_init_query(struct ufs_hba *hba,
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/**
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* ufshcd_query_flag() - API function for sending flag query requests
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*/
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int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
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enum flag_idn idn, bool *flag_res)
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static int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
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enum flag_idn idn, bool *flag_res)
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{
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struct ufs_query_req *request = NULL;
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struct ufs_query_res *response = NULL;
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@@ -1170,9 +1167,9 @@ out:
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/**
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* ufshcd_query_descriptor_retry - API function for sending descriptor requests
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*/
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int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode,
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enum desc_idn idn, u8 index, u8 selector,
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u8 *desc_buf, int *buf_len)
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static int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode,
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enum desc_idn idn, u8 index, u8 selector,
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u8 *desc_buf, int *buf_len)
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{
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int err;
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int retries;
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@@ -1264,8 +1261,8 @@ static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
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* ufshcd_map_desc_id_to_length - map descriptor IDN to its length
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*
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*/
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int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
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int *desc_len)
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static int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
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int *desc_len)
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{
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switch (desc_id) {
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case QUERY_DESC_IDN_DEVICE:
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@@ -1302,15 +1299,14 @@ int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
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}
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return 0;
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}
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EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
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/**
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* ufshcd_read_desc_param - read the specified descriptor parameter
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*
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*/
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int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id,
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int desc_index, u8 param_offset, u8 *param_read_buf,
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u8 param_size)
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static int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id,
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int desc_index, u8 param_offset,
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u8 *param_read_buf, u8 param_size)
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{
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int ret;
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u8 *desc_buf;
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@@ -1569,8 +1565,8 @@ static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
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* ufshcd_read_string_desc - read string descriptor
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*
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*/
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int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
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u8 *buf, u32 size, bool ascii)
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static int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
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u8 *buf, u32 size, bool ascii)
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{
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int err = 0;
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@@ -1881,7 +1877,7 @@ static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
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hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
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}
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int ufs_start(struct ufs_hba *hba)
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static int ufs_start(struct ufs_hba *hba)
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{
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struct ufs_dev_desc card = {0};
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int ret;
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@@ -1962,7 +1958,7 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
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ufshcd_ops_init(hba);
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/* Read capabilties registers */
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/* Read capabilities registers */
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hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
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if (hba->quirks & UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS)
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hba->capabilities &= ~MASK_64_ADDRESSING_SUPPORT;
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@@ -2001,7 +1997,7 @@ int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
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REG_INTERRUPT_STATUS);
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ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
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mb();
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mb(); /* flush previous writes */
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/* Reset the attached device */
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ufshcd_device_reset(hba);
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@@ -4,6 +4,7 @@
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#include <linux/types.h>
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#include <asm/io.h>
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#include "ufshci.h"
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#include "unipro.h"
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struct udevice;
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@@ -14,11 +15,6 @@ struct udevice;
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#define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
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#define UFS_MAX_LUNS 0x7F
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enum {
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TASK_REQ_UPIU_SIZE_DWORDS = 8,
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TASK_RSP_UPIU_SIZE_DWORDS = 8,
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ALIGNED_UPIU_SIZE = 512,
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};
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/* UFS device power modes */
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enum ufs_dev_pwr_mode {
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@@ -84,44 +80,6 @@ enum {
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/* Offset of the response code in the UPIU header */
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#define UPIU_RSP_CODE_OFFSET 8
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/* To accommodate UFS2.0 required Command type */
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enum {
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UTP_CMD_TYPE_UFS_STORAGE = 0x1,
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};
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enum {
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UTP_SCSI_COMMAND = 0x00000000,
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UTP_NATIVE_UFS_COMMAND = 0x10000000,
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UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
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UTP_REQ_DESC_INT_CMD = 0x01000000,
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};
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/* UTP Transfer Request Data Direction (DD) */
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enum {
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UTP_NO_DATA_TRANSFER = 0x00000000,
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UTP_HOST_TO_DEVICE = 0x02000000,
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UTP_DEVICE_TO_HOST = 0x04000000,
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};
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/* Overall command status values */
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enum {
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OCS_SUCCESS = 0x0,
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OCS_INVALID_CMD_TABLE_ATTR = 0x1,
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OCS_INVALID_PRDT_ATTR = 0x2,
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OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
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OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
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OCS_PEER_COMM_FAILURE = 0x5,
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OCS_ABORTED = 0x6,
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OCS_FATAL_ERROR = 0x7,
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OCS_INVALID_COMMAND_STATUS = 0x0F,
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MASK_OCS = 0x0F,
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};
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/* The maximum length of the data byte count field in the PRDT is 256KB */
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#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
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/* The granularity of the data byte count field in the PRDT is 32-bit */
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#define PRDT_DATA_BYTE_COUNT_PAD 4
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#define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
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#define QUERY_DESC_MAX_SIZE 255
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#define QUERY_DESC_MIN_SIZE 2
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@@ -130,8 +88,8 @@ enum {
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(sizeof(struct utp_upiu_header)))
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#define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
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#define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
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cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
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(byte1 << 8) | (byte0))
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cpu_to_be32(((byte3) << 24) | ((byte2) << 16) |\
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((byte1) << 8) | (byte0))
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/*
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* UFS Protocol Information Unit related definitions
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*/
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@@ -297,79 +255,6 @@ enum desc_header_offset {
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QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
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};
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struct ufshcd_sg_entry {
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__le32 base_addr;
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__le32 upper_addr;
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__le32 reserved;
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__le32 size;
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};
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#define MAX_BUFF 128
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/**
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* struct utp_transfer_cmd_desc - UFS Command Descriptor structure
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* @command_upiu: Command UPIU Frame address
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* @response_upiu: Response UPIU Frame address
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* @prd_table: Physical Region Descriptor
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*/
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struct utp_transfer_cmd_desc {
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u8 command_upiu[ALIGNED_UPIU_SIZE];
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u8 response_upiu[ALIGNED_UPIU_SIZE];
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struct ufshcd_sg_entry prd_table[MAX_BUFF];
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};
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/**
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* struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
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* @dword0: Descriptor Header DW0
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* @dword1: Descriptor Header DW1
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* @dword2: Descriptor Header DW2
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* @dword3: Descriptor Header DW3
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*/
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struct request_desc_header {
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__le32 dword_0;
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__le32 dword_1;
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__le32 dword_2;
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__le32 dword_3;
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};
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/**
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* struct utp_transfer_req_desc - UTRD structure
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* @header: UTRD header DW-0 to DW-3
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* @command_desc_base_addr_lo: UCD base address low DW-4
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* @command_desc_base_addr_hi: UCD base address high DW-5
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* @response_upiu_length: response UPIU length DW-6
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* @response_upiu_offset: response UPIU offset DW-6
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* @prd_table_length: Physical region descriptor length DW-7
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* @prd_table_offset: Physical region descriptor offset DW-7
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*/
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struct utp_transfer_req_desc {
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/* DW 0-3 */
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struct request_desc_header header;
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/* DW 4-5*/
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__le32 command_desc_base_addr_lo;
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__le32 command_desc_base_addr_hi;
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/* DW 6 */
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__le16 response_upiu_length;
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__le16 response_upiu_offset;
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/* DW 7 */
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__le16 prd_table_length;
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__le16 prd_table_offset;
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};
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/**
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* struct utp_upiu_header - UPIU header structure
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* @dword_0: UPIU header DW-0
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* @dword_1: UPIU header DW-1
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* @dword_2: UPIU header DW-2
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*/
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struct utp_upiu_header {
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__be32 dword_0;
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__be32 dword_1;
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__be32 dword_2;
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};
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/**
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* struct utp_upiu_query - upiu request buffer structure for
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* query request.
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@@ -403,27 +288,6 @@ struct utp_upiu_cmd {
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u8 cdb[UFS_CDB_SIZE];
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};
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/*
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* UTMRD structure.
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*/
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struct utp_task_req_desc {
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/* DW 0-3 */
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struct request_desc_header header;
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/* DW 4-11 - Task request UPIU structure */
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struct utp_upiu_header req_header;
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__be32 input_param1;
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__be32 input_param2;
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__be32 input_param3;
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__be32 __reserved1[2];
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/* DW 12-19 - Task Management Response UPIU structure */
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struct utp_upiu_header rsp_header;
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__be32 output_param1;
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__be32 output_param2;
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__be32 __reserved2[3];
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};
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/**
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* struct utp_upiu_req - general upiu request structure
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* @header:UPIU header structure DW-0 to DW-2
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@@ -551,63 +415,6 @@ struct uic_command {
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int result;
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};
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/* GenSelectorIndex calculation macros for M-PHY attributes */
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#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
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#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
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#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
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((sel) & 0xFFFF))
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#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
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#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
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#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
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/* Link Status*/
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enum link_status {
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UFSHCD_LINK_IS_DOWN = 1,
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UFSHCD_LINK_IS_UP = 2,
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};
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#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
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((sel) & 0xFFFF))
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#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
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#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
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#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
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/* UIC Commands */
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enum uic_cmd_dme {
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UIC_CMD_DME_GET = 0x01,
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UIC_CMD_DME_SET = 0x02,
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UIC_CMD_DME_PEER_GET = 0x03,
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UIC_CMD_DME_PEER_SET = 0x04,
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UIC_CMD_DME_POWERON = 0x10,
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UIC_CMD_DME_POWEROFF = 0x11,
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UIC_CMD_DME_ENABLE = 0x12,
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UIC_CMD_DME_RESET = 0x14,
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UIC_CMD_DME_END_PT_RST = 0x15,
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UIC_CMD_DME_LINK_STARTUP = 0x16,
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UIC_CMD_DME_HIBER_ENTER = 0x17,
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UIC_CMD_DME_HIBER_EXIT = 0x18,
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UIC_CMD_DME_TEST_MODE = 0x1A,
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};
|
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/* UIC Config result code / Generic error code */
|
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enum {
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UIC_CMD_RESULT_SUCCESS = 0x00,
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UIC_CMD_RESULT_INVALID_ATTR = 0x01,
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UIC_CMD_RESULT_FAILURE = 0x01,
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UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
|
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UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
|
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UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
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UIC_CMD_RESULT_BAD_INDEX = 0x05,
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UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
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UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
|
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UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
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UIC_CMD_RESULT_BUSY = 0x09,
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UIC_CMD_RESULT_DME_FAILURE = 0x0A,
|
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};
|
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|
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#define MASK_UIC_COMMAND_RESULT 0xFF
|
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|
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/* Host <-> Device UniPro Link state */
|
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enum uic_link_state {
|
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UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
|
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@@ -915,7 +722,7 @@ static inline int ufshcd_ops_get_max_pwr_mode(struct ufs_hba *hba,
|
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}
|
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|
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static inline int ufshcd_ops_hce_enable_notify(struct ufs_hba *hba,
|
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bool status)
|
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bool status)
|
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{
|
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if (hba->ops && hba->ops->hce_enable_notify)
|
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return hba->ops->hce_enable_notify(hba, status);
|
||||
@@ -940,17 +747,6 @@ static inline int ufshcd_vops_device_reset(struct ufs_hba *hba)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Controller UFSHCI version */
|
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enum {
|
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UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
|
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UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
|
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UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
|
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UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
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UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
|
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UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */
|
||||
UFSHCI_VERSION_40 = 0x00000400, /* 4.0 */
|
||||
};
|
||||
|
||||
/* Interrupt disable masks */
|
||||
enum {
|
||||
/* Interrupt disable mask for UFSHCI v1.0 */
|
||||
@@ -964,123 +760,6 @@ enum {
|
||||
INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
|
||||
};
|
||||
|
||||
/* UFSHCI Registers */
|
||||
enum {
|
||||
REG_CONTROLLER_CAPABILITIES = 0x00,
|
||||
REG_UFS_VERSION = 0x08,
|
||||
REG_CONTROLLER_DEV_ID = 0x10,
|
||||
REG_CONTROLLER_PROD_ID = 0x14,
|
||||
REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
|
||||
REG_INTERRUPT_STATUS = 0x20,
|
||||
REG_INTERRUPT_ENABLE = 0x24,
|
||||
REG_CONTROLLER_STATUS = 0x30,
|
||||
REG_CONTROLLER_ENABLE = 0x34,
|
||||
REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
|
||||
REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
|
||||
REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
|
||||
REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
|
||||
REG_UIC_ERROR_CODE_DME = 0x48,
|
||||
REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
|
||||
REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
|
||||
REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
|
||||
REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
|
||||
REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
|
||||
REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
|
||||
REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
|
||||
REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
|
||||
REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
|
||||
REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
|
||||
REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
|
||||
REG_UIC_COMMAND = 0x90,
|
||||
REG_UIC_COMMAND_ARG_1 = 0x94,
|
||||
REG_UIC_COMMAND_ARG_2 = 0x98,
|
||||
REG_UIC_COMMAND_ARG_3 = 0x9C,
|
||||
|
||||
UFSHCI_REG_SPACE_SIZE = 0xA0,
|
||||
|
||||
REG_UFS_CCAP = 0x100,
|
||||
REG_UFS_CRYPTOCAP = 0x104,
|
||||
|
||||
UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
|
||||
};
|
||||
|
||||
/* Controller capability masks */
|
||||
enum {
|
||||
MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
|
||||
MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
|
||||
MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
|
||||
MASK_64_ADDRESSING_SUPPORT = 0x01000000,
|
||||
MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
|
||||
MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
|
||||
};
|
||||
|
||||
/* Interrupt Status 20h */
|
||||
#define UTP_TRANSFER_REQ_COMPL 0x1
|
||||
#define UIC_DME_END_PT_RESET 0x2
|
||||
#define UIC_ERROR 0x4
|
||||
#define UIC_TEST_MODE 0x8
|
||||
#define UIC_POWER_MODE 0x10
|
||||
#define UIC_HIBERNATE_EXIT 0x20
|
||||
#define UIC_HIBERNATE_ENTER 0x40
|
||||
#define UIC_LINK_LOST 0x80
|
||||
#define UIC_LINK_STARTUP 0x100
|
||||
#define UTP_TASK_REQ_COMPL 0x200
|
||||
#define UIC_COMMAND_COMPL 0x400
|
||||
#define DEVICE_FATAL_ERROR 0x800
|
||||
#define CONTROLLER_FATAL_ERROR 0x10000
|
||||
#define SYSTEM_BUS_FATAL_ERROR 0x20000
|
||||
|
||||
#define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\
|
||||
UIC_HIBERNATE_EXIT |\
|
||||
UIC_POWER_MODE)
|
||||
|
||||
#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UIC_POWER_MODE)
|
||||
|
||||
#define UFSHCD_ERROR_MASK (UIC_ERROR |\
|
||||
DEVICE_FATAL_ERROR |\
|
||||
CONTROLLER_FATAL_ERROR |\
|
||||
SYSTEM_BUS_FATAL_ERROR)
|
||||
|
||||
#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
|
||||
CONTROLLER_FATAL_ERROR |\
|
||||
SYSTEM_BUS_FATAL_ERROR)
|
||||
|
||||
/* Host Controller Enable 0x34h */
|
||||
#define CONTROLLER_ENABLE 0x1
|
||||
#define CONTROLLER_DISABLE 0x0
|
||||
/* HCS - Host Controller Status 30h */
|
||||
#define DEVICE_PRESENT 0x1
|
||||
#define UTP_TRANSFER_REQ_LIST_READY 0x2
|
||||
#define UTP_TASK_REQ_LIST_READY 0x4
|
||||
#define UIC_COMMAND_READY 0x8
|
||||
#define HOST_ERROR_INDICATOR 0x10
|
||||
#define DEVICE_ERROR_INDICATOR 0x20
|
||||
#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
|
||||
|
||||
#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
|
||||
UTP_TASK_REQ_LIST_READY |\
|
||||
UIC_COMMAND_READY)
|
||||
|
||||
enum {
|
||||
PWR_OK = 0x0,
|
||||
PWR_LOCAL = 0x01,
|
||||
PWR_REMOTE = 0x02,
|
||||
PWR_BUSY = 0x03,
|
||||
PWR_ERROR_CAP = 0x04,
|
||||
PWR_FATAL_ERROR = 0x05,
|
||||
};
|
||||
|
||||
/* UICCMD - UIC Command */
|
||||
#define COMMAND_OPCODE_MASK 0xFF
|
||||
#define GEN_SELECTOR_INDEX_MASK 0xFFFF
|
||||
|
||||
#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
|
||||
#define RESET_LEVEL 0xFF
|
||||
|
||||
#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
|
||||
#define CFG_RESULT_CODE_MASK 0xFF
|
||||
#define GENERIC_ERROR_CODE_MASK 0xFF
|
||||
|
||||
#define ufshcd_writel(hba, val, reg) \
|
||||
writel((val), (hba)->mmio_base + (reg))
|
||||
#define ufshcd_readl(hba, reg) \
|
||||
@@ -1103,12 +782,6 @@ static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
|
||||
ufshcd_writel(hba, tmp, reg);
|
||||
}
|
||||
|
||||
/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
|
||||
#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
|
||||
|
||||
/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
|
||||
#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
|
||||
|
||||
int ufshcd_probe(struct udevice *dev, struct ufs_hba_ops *hba_ops);
|
||||
|
||||
#endif
|
||||
|
||||
469
drivers/ufs/ufshci.h
Normal file
469
drivers/ufs/ufshci.h
Normal file
@@ -0,0 +1,469 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
#ifndef __UFSHCI_H
|
||||
#define __UFSHCI_H
|
||||
|
||||
enum {
|
||||
TASK_REQ_UPIU_SIZE_DWORDS = 8,
|
||||
TASK_RSP_UPIU_SIZE_DWORDS = 8,
|
||||
ALIGNED_UPIU_SIZE = 512,
|
||||
};
|
||||
|
||||
/* UFSHCI Registers */
|
||||
enum {
|
||||
REG_CONTROLLER_CAPABILITIES = 0x00,
|
||||
REG_MCQCAP = 0x04,
|
||||
REG_UFS_VERSION = 0x08,
|
||||
REG_EXT_CONTROLLER_CAPABILITIES = 0x0C,
|
||||
REG_CONTROLLER_PID = 0x10,
|
||||
REG_CONTROLLER_MID = 0x14,
|
||||
REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
|
||||
REG_INTERRUPT_STATUS = 0x20,
|
||||
REG_INTERRUPT_ENABLE = 0x24,
|
||||
REG_CONTROLLER_STATUS = 0x30,
|
||||
REG_CONTROLLER_ENABLE = 0x34,
|
||||
REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
|
||||
REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
|
||||
REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
|
||||
REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
|
||||
REG_UIC_ERROR_CODE_DME = 0x48,
|
||||
REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
|
||||
REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
|
||||
REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
|
||||
REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
|
||||
REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
|
||||
REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
|
||||
REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
|
||||
REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
|
||||
REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
|
||||
REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
|
||||
REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
|
||||
REG_UIC_COMMAND = 0x90,
|
||||
REG_UIC_COMMAND_ARG_1 = 0x94,
|
||||
REG_UIC_COMMAND_ARG_2 = 0x98,
|
||||
REG_UIC_COMMAND_ARG_3 = 0x9C,
|
||||
|
||||
UFSHCI_REG_SPACE_SIZE = 0xA0,
|
||||
|
||||
REG_UFS_CCAP = 0x100,
|
||||
REG_UFS_CRYPTOCAP = 0x104,
|
||||
|
||||
REG_UFS_MEM_CFG = 0x300,
|
||||
REG_UFS_MCQ_CFG = 0x380,
|
||||
REG_UFS_ESILBA = 0x384,
|
||||
REG_UFS_ESIUBA = 0x388,
|
||||
UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
|
||||
};
|
||||
|
||||
/* Controller capability masks */
|
||||
enum {
|
||||
MASK_TRANSFER_REQUESTS_SLOTS_SDB = 0x0000001F,
|
||||
MASK_TRANSFER_REQUESTS_SLOTS_MCQ = 0x000000FF,
|
||||
MASK_NUMBER_OUTSTANDING_RTT = 0x0000FF00,
|
||||
MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
|
||||
MASK_EHSLUTRD_SUPPORTED = 0x00400000,
|
||||
MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
|
||||
MASK_64_ADDRESSING_SUPPORT = 0x01000000,
|
||||
MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
|
||||
MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
|
||||
MASK_CRYPTO_SUPPORT = 0x10000000,
|
||||
MASK_LSDB_SUPPORT = 0x20000000,
|
||||
MASK_MCQ_SUPPORT = 0x40000000,
|
||||
};
|
||||
|
||||
/* MCQ capability mask */
|
||||
enum {
|
||||
MASK_EXT_IID_SUPPORT = 0x00000400,
|
||||
};
|
||||
|
||||
enum {
|
||||
REG_SQATTR = 0x0,
|
||||
REG_SQLBA = 0x4,
|
||||
REG_SQUBA = 0x8,
|
||||
REG_SQDAO = 0xC,
|
||||
REG_SQISAO = 0x10,
|
||||
|
||||
REG_CQATTR = 0x20,
|
||||
REG_CQLBA = 0x24,
|
||||
REG_CQUBA = 0x28,
|
||||
REG_CQDAO = 0x2C,
|
||||
REG_CQISAO = 0x30,
|
||||
};
|
||||
|
||||
enum {
|
||||
REG_SQHP = 0x0,
|
||||
REG_SQTP = 0x4,
|
||||
REG_SQRTC = 0x8,
|
||||
REG_SQCTI = 0xC,
|
||||
REG_SQRTS = 0x10,
|
||||
};
|
||||
|
||||
enum {
|
||||
REG_CQHP = 0x0,
|
||||
REG_CQTP = 0x4,
|
||||
};
|
||||
|
||||
enum {
|
||||
REG_CQIS = 0x0,
|
||||
REG_CQIE = 0x4,
|
||||
};
|
||||
|
||||
enum {
|
||||
SQ_START = 0x0,
|
||||
SQ_STOP = 0x1,
|
||||
SQ_ICU = 0x2,
|
||||
};
|
||||
|
||||
enum {
|
||||
SQ_STS = 0x1,
|
||||
SQ_CUS = 0x2,
|
||||
};
|
||||
|
||||
#define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4)
|
||||
#define UFS_MASK(mask, offset) ((mask) << (offset))
|
||||
|
||||
/* UFS Version 08h */
|
||||
#define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
|
||||
#define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
|
||||
|
||||
/* Controller UFSHCI version */
|
||||
enum {
|
||||
UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
|
||||
UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
|
||||
UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
|
||||
UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
|
||||
UFSHCI_VERSION_30 = 0x00000300, /* 3.0 */
|
||||
UFSHCI_VERSION_31 = 0x00000310, /* 3.1 */
|
||||
UFSHCI_VERSION_40 = 0x00000400, /* 4.0 */
|
||||
};
|
||||
|
||||
/*
|
||||
* IS - Interrupt Status - 20h
|
||||
*/
|
||||
#define UTP_TRANSFER_REQ_COMPL 0x1
|
||||
#define UIC_DME_END_PT_RESET 0x2
|
||||
#define UIC_ERROR 0x4
|
||||
#define UIC_TEST_MODE 0x8
|
||||
#define UIC_POWER_MODE 0x10
|
||||
#define UIC_HIBERNATE_EXIT 0x20
|
||||
#define UIC_HIBERNATE_ENTER 0x40
|
||||
#define UIC_LINK_LOST 0x80
|
||||
#define UIC_LINK_STARTUP 0x100
|
||||
#define UTP_TASK_REQ_COMPL 0x200
|
||||
#define UIC_COMMAND_COMPL 0x400
|
||||
#define DEVICE_FATAL_ERROR 0x800
|
||||
#define CONTROLLER_FATAL_ERROR 0x10000
|
||||
#define SYSTEM_BUS_FATAL_ERROR 0x20000
|
||||
#define CRYPTO_ENGINE_FATAL_ERROR 0x40000
|
||||
#define MCQ_CQ_EVENT_STATUS 0x100000
|
||||
|
||||
#define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
|
||||
UIC_HIBERNATE_EXIT)
|
||||
|
||||
#define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
|
||||
UIC_POWER_MODE)
|
||||
|
||||
#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
|
||||
|
||||
#define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS)
|
||||
|
||||
#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
|
||||
CONTROLLER_FATAL_ERROR |\
|
||||
SYSTEM_BUS_FATAL_ERROR |\
|
||||
CRYPTO_ENGINE_FATAL_ERROR |\
|
||||
UIC_LINK_LOST)
|
||||
|
||||
/* HCS - Host Controller Status 30h */
|
||||
#define DEVICE_PRESENT 0x1
|
||||
#define UTP_TRANSFER_REQ_LIST_READY 0x2
|
||||
#define UTP_TASK_REQ_LIST_READY 0x4
|
||||
#define UIC_COMMAND_READY 0x8
|
||||
#define HOST_ERROR_INDICATOR 0x10
|
||||
#define DEVICE_ERROR_INDICATOR 0x20
|
||||
#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
|
||||
|
||||
#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
|
||||
UTP_TASK_REQ_LIST_READY |\
|
||||
UIC_COMMAND_READY)
|
||||
|
||||
enum {
|
||||
PWR_OK = 0x0,
|
||||
PWR_LOCAL = 0x01,
|
||||
PWR_REMOTE = 0x02,
|
||||
PWR_BUSY = 0x03,
|
||||
PWR_ERROR_CAP = 0x04,
|
||||
PWR_FATAL_ERROR = 0x05,
|
||||
};
|
||||
|
||||
/* HCE - Host Controller Enable 34h */
|
||||
#define CONTROLLER_ENABLE 0x1
|
||||
#define CONTROLLER_DISABLE 0x0
|
||||
#define CRYPTO_GENERAL_ENABLE 0x2
|
||||
|
||||
/* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
|
||||
#define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
|
||||
#define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
|
||||
#define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
|
||||
#define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
|
||||
|
||||
/* UECDL - Host UIC Error Code Data Link Layer 3Ch */
|
||||
#define UIC_DATA_LINK_LAYER_ERROR 0x80000000
|
||||
#define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
|
||||
#define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
|
||||
#define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
|
||||
#define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
|
||||
#define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
|
||||
#define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
|
||||
#define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
|
||||
#define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
|
||||
|
||||
/* UECN - Host UIC Error Code Network Layer 40h */
|
||||
#define UIC_NETWORK_LAYER_ERROR 0x80000000
|
||||
#define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
|
||||
#define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
|
||||
#define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
|
||||
#define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
|
||||
|
||||
/* UECT - Host UIC Error Code Transport Layer 44h */
|
||||
#define UIC_TRANSPORT_LAYER_ERROR 0x80000000
|
||||
#define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
|
||||
#define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
|
||||
#define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
|
||||
#define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
|
||||
#define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
|
||||
#define UIC_TRANSPORT_BAD_TC 0x10
|
||||
#define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
|
||||
#define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
|
||||
|
||||
/* UECDME - Host UIC Error Code DME 48h */
|
||||
#define UIC_DME_ERROR 0x80000000
|
||||
#define UIC_DME_ERROR_CODE_MASK 0x1
|
||||
|
||||
/* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
|
||||
#define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
|
||||
#define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
|
||||
#define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
|
||||
#define INT_AGGR_STATUS_BIT 0x100000
|
||||
#define INT_AGGR_PARAM_WRITE 0x1000000
|
||||
#define INT_AGGR_ENABLE 0x80000000
|
||||
|
||||
/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
|
||||
#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
|
||||
|
||||
/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
|
||||
#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
|
||||
|
||||
/* REG_UFS_MEM_CFG - Global Config Registers 300h */
|
||||
#define MCQ_MODE_SELECT BIT(0)
|
||||
|
||||
/* CQISy - CQ y Interrupt Status Register */
|
||||
#define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1
|
||||
|
||||
/* UICCMD - UIC Command */
|
||||
#define COMMAND_OPCODE_MASK 0xFF
|
||||
#define GEN_SELECTOR_INDEX_MASK 0xFFFF
|
||||
|
||||
#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
|
||||
#define RESET_LEVEL 0xFF
|
||||
|
||||
#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
|
||||
#define CFG_RESULT_CODE_MASK 0xFF
|
||||
#define GENERIC_ERROR_CODE_MASK 0xFF
|
||||
|
||||
/* GenSelectorIndex calculation macros for M-PHY attributes */
|
||||
#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
|
||||
#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
|
||||
|
||||
#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
|
||||
((sel) & 0xFFFF))
|
||||
#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
|
||||
#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
|
||||
#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
|
||||
|
||||
/* Link Status*/
|
||||
enum link_status {
|
||||
UFSHCD_LINK_IS_DOWN = 1,
|
||||
UFSHCD_LINK_IS_UP = 2,
|
||||
};
|
||||
|
||||
/* UIC Commands */
|
||||
enum uic_cmd_dme {
|
||||
UIC_CMD_DME_GET = 0x01,
|
||||
UIC_CMD_DME_SET = 0x02,
|
||||
UIC_CMD_DME_PEER_GET = 0x03,
|
||||
UIC_CMD_DME_PEER_SET = 0x04,
|
||||
UIC_CMD_DME_POWERON = 0x10,
|
||||
UIC_CMD_DME_POWEROFF = 0x11,
|
||||
UIC_CMD_DME_ENABLE = 0x12,
|
||||
UIC_CMD_DME_RESET = 0x14,
|
||||
UIC_CMD_DME_END_PT_RST = 0x15,
|
||||
UIC_CMD_DME_LINK_STARTUP = 0x16,
|
||||
UIC_CMD_DME_HIBER_ENTER = 0x17,
|
||||
UIC_CMD_DME_HIBER_EXIT = 0x18,
|
||||
UIC_CMD_DME_TEST_MODE = 0x1A,
|
||||
};
|
||||
|
||||
/* UIC Config result code / Generic error code */
|
||||
enum {
|
||||
UIC_CMD_RESULT_SUCCESS = 0x00,
|
||||
UIC_CMD_RESULT_INVALID_ATTR = 0x01,
|
||||
UIC_CMD_RESULT_FAILURE = 0x01,
|
||||
UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
|
||||
UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
|
||||
UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
|
||||
UIC_CMD_RESULT_BAD_INDEX = 0x05,
|
||||
UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
|
||||
UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
|
||||
UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
|
||||
UIC_CMD_RESULT_BUSY = 0x09,
|
||||
UIC_CMD_RESULT_DME_FAILURE = 0x0A,
|
||||
};
|
||||
|
||||
#define MASK_UIC_COMMAND_RESULT 0xFF
|
||||
|
||||
#define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
|
||||
#define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
|
||||
|
||||
/*
|
||||
* Request Descriptor Definitions
|
||||
*/
|
||||
|
||||
/* To accommodate UFS2.0 required Command type */
|
||||
enum {
|
||||
UTP_CMD_TYPE_UFS_STORAGE = 0x1,
|
||||
};
|
||||
|
||||
enum {
|
||||
UTP_SCSI_COMMAND = 0x00000000,
|
||||
UTP_REQ_DESC_INT_CMD = 0x01000000,
|
||||
UTP_NATIVE_UFS_COMMAND = 0x10000000,
|
||||
UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
|
||||
};
|
||||
|
||||
/* UTP Transfer Request Data Direction (DD) */
|
||||
enum utp_data_direction {
|
||||
UTP_NO_DATA_TRANSFER = 0,
|
||||
UTP_HOST_TO_DEVICE = 1,
|
||||
UTP_DEVICE_TO_HOST = 2,
|
||||
};
|
||||
|
||||
/* Overall command status values */
|
||||
enum utp_ocs {
|
||||
OCS_SUCCESS = 0x0,
|
||||
OCS_INVALID_CMD_TABLE_ATTR = 0x1,
|
||||
OCS_INVALID_PRDT_ATTR = 0x2,
|
||||
OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
|
||||
OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
|
||||
OCS_PEER_COMM_FAILURE = 0x5,
|
||||
OCS_ABORTED = 0x6,
|
||||
OCS_FATAL_ERROR = 0x7,
|
||||
OCS_DEVICE_FATAL_ERROR = 0x8,
|
||||
OCS_INVALID_CRYPTO_CONFIG = 0x9,
|
||||
OCS_GENERAL_CRYPTO_ERROR = 0xA,
|
||||
OCS_INVALID_COMMAND_STATUS = 0x0F,
|
||||
};
|
||||
|
||||
enum {
|
||||
MASK_OCS = 0x0F,
|
||||
};
|
||||
|
||||
/* The maximum length of the data byte count field in the PRDT is 256KB */
|
||||
#define PRDT_DATA_BYTE_COUNT_MAX SZ_256K
|
||||
/* The granularity of the data byte count field in the PRDT is 32-bit */
|
||||
#define PRDT_DATA_BYTE_COUNT_PAD 4
|
||||
|
||||
|
||||
struct ufshcd_sg_entry {
|
||||
__le32 base_addr;
|
||||
__le32 upper_addr;
|
||||
__le32 reserved;
|
||||
__le32 size;
|
||||
};
|
||||
|
||||
#define MAX_BUFF 128
|
||||
/**
|
||||
* struct utp_transfer_cmd_desc - UFS Command Descriptor structure
|
||||
* @command_upiu: Command UPIU Frame address
|
||||
* @response_upiu: Response UPIU Frame address
|
||||
* @prd_table: Physical Region Descriptor
|
||||
*/
|
||||
struct utp_transfer_cmd_desc {
|
||||
u8 command_upiu[ALIGNED_UPIU_SIZE];
|
||||
u8 response_upiu[ALIGNED_UPIU_SIZE];
|
||||
struct ufshcd_sg_entry prd_table[MAX_BUFF];
|
||||
};
|
||||
|
||||
/**
|
||||
* struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
|
||||
* @dword0: Descriptor Header DW0
|
||||
* @dword1: Descriptor Header DW1
|
||||
* @dword2: Descriptor Header DW2
|
||||
* @dword3: Descriptor Header DW3
|
||||
*/
|
||||
struct request_desc_header {
|
||||
__le32 dword_0;
|
||||
__le32 dword_1;
|
||||
__le32 dword_2;
|
||||
__le32 dword_3;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct utp_transfer_req_desc - UTRD structure
|
||||
* @header: UTRD header DW-0 to DW-3
|
||||
* @command_desc_base_addr_lo: UCD base address low DW-4
|
||||
* @command_desc_base_addr_hi: UCD base address high DW-5
|
||||
* @response_upiu_length: response UPIU length DW-6
|
||||
* @response_upiu_offset: response UPIU offset DW-6
|
||||
* @prd_table_length: Physical region descriptor length DW-7
|
||||
* @prd_table_offset: Physical region descriptor offset DW-7
|
||||
*/
|
||||
struct utp_transfer_req_desc {
|
||||
/* DW 0-3 */
|
||||
struct request_desc_header header;
|
||||
|
||||
/* DW 4-5*/
|
||||
__le32 command_desc_base_addr_lo;
|
||||
__le32 command_desc_base_addr_hi;
|
||||
|
||||
/* DW 6 */
|
||||
__le16 response_upiu_length;
|
||||
__le16 response_upiu_offset;
|
||||
|
||||
/* DW 7 */
|
||||
__le16 prd_table_length;
|
||||
__le16 prd_table_offset;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct utp_upiu_header - UPIU header structure
|
||||
* @dword_0: UPIU header DW-0
|
||||
* @dword_1: UPIU header DW-1
|
||||
* @dword_2: UPIU header DW-2
|
||||
*/
|
||||
struct utp_upiu_header {
|
||||
__be32 dword_0;
|
||||
__be32 dword_1;
|
||||
__be32 dword_2;
|
||||
};
|
||||
|
||||
/*
|
||||
* UTMRD structure.
|
||||
*/
|
||||
struct utp_task_req_desc {
|
||||
/* DW 0-3 */
|
||||
struct request_desc_header header;
|
||||
|
||||
/* DW 4-11 - Task request UPIU structure */
|
||||
struct utp_upiu_header req_header;
|
||||
__be32 input_param1;
|
||||
__be32 input_param2;
|
||||
__be32 input_param3;
|
||||
__be32 __reserved1[2];
|
||||
|
||||
/* DW 12-19 - Task Management Response UPIU structure */
|
||||
struct utp_upiu_header rsp_header;
|
||||
__be32 output_param1;
|
||||
__be32 output_param2;
|
||||
__be32 __reserved2[3];
|
||||
};
|
||||
|
||||
#endif
|
||||
@@ -34,6 +34,18 @@
|
||||
/*
|
||||
* M-RX Configuration Attributes
|
||||
*/
|
||||
#define RX_HS_G1_SYNC_LENGTH_CAP 0x008B
|
||||
#define RX_HS_G1_PREP_LENGTH_CAP 0x008C
|
||||
#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F
|
||||
#define RX_HIBERN8TIME_CAPABILITY 0x0092
|
||||
#define RX_HS_G2_SYNC_LENGTH_CAP 0x0094
|
||||
#define RX_HS_G3_SYNC_LENGTH_CAP 0x0095
|
||||
#define RX_HS_G2_PREP_LENGTH_CAP 0x0096
|
||||
#define RX_HS_G3_PREP_LENGTH_CAP 0x0097
|
||||
#define RX_ADV_GRANULARITY_CAP 0x0098
|
||||
#define RX_HIBERN8TIME_CAP 0x0092
|
||||
#define RX_ADV_HIBERN8TIME_CAP 0x0099
|
||||
#define RX_ADV_MIN_ACTIVATETIME_CAP 0x009A
|
||||
#define RX_MODE 0x00A1
|
||||
#define RX_HSRATE_SERIES 0x00A2
|
||||
#define RX_HSGEAR 0x00A3
|
||||
@@ -42,24 +54,27 @@
|
||||
#define RX_HS_UNTERMINATED_ENABLE 0x00A6
|
||||
#define RX_ENTER_HIBERN8 0x00A7
|
||||
#define RX_BYPASS_8B10B_ENABLE 0x00A8
|
||||
#define RX_TERMINATION_FORCE_ENABLE 0x0089
|
||||
#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F
|
||||
#define RX_HIBERN8TIME_CAPABILITY 0x0092
|
||||
#define RX_TERMINATION_FORCE_ENABLE 0x00A9
|
||||
#define RXCALCTRL 0x00B4
|
||||
#define RXSQCTRL 0x00B5
|
||||
#define CFGRXCDR8 0x00BA
|
||||
#define CFGRXOVR8 0x00BD
|
||||
#define CFGRXOVR6 0x00BF
|
||||
#define RXDIRECTCTRL2 0x00C7
|
||||
#define CFGRXOVR4 0x00E9
|
||||
#define RX_REFCLKFREQ 0x00EB
|
||||
#define RX_CFGCLKFREQVAL 0x00EC
|
||||
#define CFGWIDEINLN 0x00F0
|
||||
#define CFGRXCDR8 0x00BA
|
||||
#define ENARXDIRECTCFG4 0x00F2
|
||||
#define CFGRXOVR8 0x00BD
|
||||
#define RXDIRECTCTRL2 0x00C7
|
||||
#define ENARXDIRECTCFG3 0x00F3
|
||||
#define RXCALCTRL 0x00B4
|
||||
#define ENARXDIRECTCFG2 0x00F4
|
||||
#define CFGRXOVR4 0x00E9
|
||||
#define RXSQCTRL 0x00B5
|
||||
#define CFGRXOVR6 0x00BF
|
||||
|
||||
#define is_mphy_tx_attr(attr) (attr < RX_MODE)
|
||||
#define is_mphy_tx_attr(attr) ((attr) < RX_MODE)
|
||||
#define RX_ADV_FINE_GRAN_STEP(x) ((((x) & 0x3) << 1) | 0x1)
|
||||
#define SYNC_LEN_FINE(x) ((x) & 0x3F)
|
||||
#define SYNC_LEN_COARSE(x) ((1 << 6) | ((x) & 0x3F))
|
||||
#define PREP_LEN(x) ((x) & 0xF)
|
||||
|
||||
#define RX_MIN_ACTIVATETIME_UNIT_US 100
|
||||
#define HIBERN8TIME_UNIT_US 100
|
||||
|
||||
@@ -77,51 +92,54 @@
|
||||
#define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8)
|
||||
#define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB)
|
||||
|
||||
#define UNIPRO_CB_OFFSET(x) (0x8000 | x)
|
||||
#define UNIPRO_CB_OFFSET(x) (0x8000 | (x))
|
||||
|
||||
/*
|
||||
* PHY Adpater attributes
|
||||
* PHY Adapter attributes
|
||||
*/
|
||||
#define PA_ACTIVETXDATALANES 0x1560
|
||||
#define PA_ACTIVERXDATALANES 0x1580
|
||||
#define PA_TXTRAILINGCLOCKS 0x1564
|
||||
#define PA_PHY_TYPE 0x1500
|
||||
#define PA_AVAILTXDATALANES 0x1520
|
||||
#define PA_AVAILRXDATALANES 0x1540
|
||||
#define PA_MINRXTRAILINGCLOCKS 0x1543
|
||||
#define PA_TXPWRSTATUS 0x1567
|
||||
#define PA_RXPWRSTATUS 0x1582
|
||||
#define PA_TXFORCECLOCK 0x1562
|
||||
#define PA_TXPWRMODE 0x1563
|
||||
#define PA_LEGACYDPHYESCDL 0x1570
|
||||
#define PA_MAXTXSPEEDFAST 0x1521
|
||||
#define PA_MAXTXSPEEDSLOW 0x1522
|
||||
#define PA_MAXRXSPEEDFAST 0x1541
|
||||
#define PA_MAXRXSPEEDSLOW 0x1542
|
||||
#define PA_TXLINKSTARTUPHS 0x1544
|
||||
#define PA_AVAILRXDATALANES 0x1540
|
||||
#define PA_MINRXTRAILINGCLOCKS 0x1543
|
||||
#define PA_LOCAL_TX_LCC_ENABLE 0x155E
|
||||
#define PA_ACTIVETXDATALANES 0x1560
|
||||
#define PA_CONNECTEDTXDATALANES 0x1561
|
||||
#define PA_TXFORCECLOCK 0x1562
|
||||
#define PA_TXPWRMODE 0x1563
|
||||
#define PA_TXTRAILINGCLOCKS 0x1564
|
||||
#define PA_TXSPEEDFAST 0x1565
|
||||
#define PA_TXSPEEDSLOW 0x1566
|
||||
#define PA_REMOTEVERINFO 0x15A0
|
||||
#define PA_TXPWRSTATUS 0x1567
|
||||
#define PA_TXGEAR 0x1568
|
||||
#define PA_TXTERMINATION 0x1569
|
||||
#define PA_HSSERIES 0x156A
|
||||
#define PA_LEGACYDPHYESCDL 0x1570
|
||||
#define PA_PWRMODE 0x1571
|
||||
#define PA_ACTIVERXDATALANES 0x1580
|
||||
#define PA_CONNECTEDRXDATALANES 0x1581
|
||||
#define PA_RXPWRSTATUS 0x1582
|
||||
#define PA_RXGEAR 0x1583
|
||||
#define PA_RXTERMINATION 0x1584
|
||||
#define PA_MAXRXPWMGEAR 0x1586
|
||||
#define PA_MAXRXHSGEAR 0x1587
|
||||
#define PA_RXHSUNTERMCAP 0x15A5
|
||||
#define PA_RXLSTERMCAP 0x15A6
|
||||
#define PA_GRANULARITY 0x15AA
|
||||
#define PA_PACPREQTIMEOUT 0x1590
|
||||
#define PA_PACPREQEOBTIMEOUT 0x1591
|
||||
#define PA_REMOTEVERINFO 0x15A0
|
||||
#define PA_LOGICALLANEMAP 0x15A1
|
||||
#define PA_SLEEPNOCONFIGTIME 0x15A2
|
||||
#define PA_STALLNOCONFIGTIME 0x15A3
|
||||
#define PA_SAVECONFIGTIME 0x15A4
|
||||
#define PA_RXHSUNTERMCAP 0x15A5
|
||||
#define PA_RXLSTERMCAP 0x15A6
|
||||
#define PA_HIBERN8TIME 0x15A7
|
||||
#define PA_LOCALVERINFO 0x15A9
|
||||
#define PA_GRANULARITY 0x15AA
|
||||
#define PA_TACTIVATE 0x15A8
|
||||
#define PA_PACPFRAMECOUNT 0x15C0
|
||||
#define PA_PACPERRORCOUNT 0x15C1
|
||||
#define PA_PHYTESTCONTROL 0x15C2
|
||||
#define PA_PWRMODEUSERDATA0 0x15B0
|
||||
#define PA_PWRMODEUSERDATA1 0x15B1
|
||||
#define PA_PWRMODEUSERDATA2 0x15B2
|
||||
@@ -134,12 +152,9 @@
|
||||
#define PA_PWRMODEUSERDATA9 0x15B9
|
||||
#define PA_PWRMODEUSERDATA10 0x15BA
|
||||
#define PA_PWRMODEUSERDATA11 0x15BB
|
||||
#define PA_CONNECTEDTXDATALANES 0x1561
|
||||
#define PA_CONNECTEDRXDATALANES 0x1581
|
||||
#define PA_LOGICALLANEMAP 0x15A1
|
||||
#define PA_SLEEPNOCONFIGTIME 0x15A2
|
||||
#define PA_STALLNOCONFIGTIME 0x15A3
|
||||
#define PA_SAVECONFIGTIME 0x15A4
|
||||
#define PA_PACPFRAMECOUNT 0x15C0
|
||||
#define PA_PACPERRORCOUNT 0x15C1
|
||||
#define PA_PHYTESTCONTROL 0x15C2
|
||||
#define PA_TXHSADAPTTYPE 0x15D4
|
||||
|
||||
/* Adapt type for PA_TXHSADAPTTYPE attribute */
|
||||
@@ -151,9 +166,9 @@
|
||||
#define PA_HIBERN8_TIME_UNIT_US 100
|
||||
|
||||
/*Other attributes*/
|
||||
#define VS_POWERSTATE 0xD083
|
||||
#define VS_MPHYCFGUPDT 0xD085
|
||||
#define VS_DEBUGOMC 0xD09E
|
||||
#define VS_POWERSTATE 0xD083
|
||||
#define VS_MPHYDISABLE 0xD0C1
|
||||
|
||||
#define PA_GRANULARITY_MIN_VAL 1
|
||||
@@ -163,7 +178,7 @@
|
||||
#define PA_MAXDATALANES 4
|
||||
|
||||
/* PA power modes */
|
||||
enum {
|
||||
enum ufs_pa_pwr_mode {
|
||||
FAST_MODE = 1,
|
||||
SLOW_MODE = 2,
|
||||
FASTAUTO_MODE = 4,
|
||||
@@ -171,8 +186,11 @@ enum {
|
||||
UNCHANGED = 7,
|
||||
};
|
||||
|
||||
#define PWRMODE_MASK 0xF
|
||||
#define PWRMODE_RX_OFFSET 4
|
||||
|
||||
/* PA TX/RX Frequency Series */
|
||||
enum {
|
||||
enum ufs_hs_gear_rate {
|
||||
PA_HS_MODE_A = 1,
|
||||
PA_HS_MODE_B = 2,
|
||||
};
|
||||
@@ -193,14 +211,24 @@ enum ufs_hs_gear_tag {
|
||||
UFS_HS_G1, /* HS Gear 1 (default for reset) */
|
||||
UFS_HS_G2, /* HS Gear 2 */
|
||||
UFS_HS_G3, /* HS Gear 3 */
|
||||
UFS_HS_G4, /* HS Gear 4 */
|
||||
UFS_HS_G5 /* HS Gear 5 */
|
||||
};
|
||||
|
||||
enum ufs_lanes {
|
||||
UFS_LANE_DONT_CHANGE, /* Don't change Lane */
|
||||
UFS_LANE_1, /* Lane 1 (default for reset) */
|
||||
UFS_LANE_2, /* Lane 2 */
|
||||
};
|
||||
|
||||
enum ufs_unipro_ver {
|
||||
UFS_UNIPRO_VER_RESERVED = 0,
|
||||
UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */
|
||||
UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */
|
||||
UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */
|
||||
UFS_UNIPRO_VER_MAX = 4, /* UniPro unsupported version */
|
||||
UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */
|
||||
UFS_UNIPRO_VER_1_61 = 4, /* UniPro version 1.61 */
|
||||
UFS_UNIPRO_VER_1_8 = 5, /* UniPro version 1.8 */
|
||||
UFS_UNIPRO_VER_MAX = 6, /* UniPro unsupported version */
|
||||
/* UniPro version field mask in PA_LOCALVERINFO */
|
||||
UFS_UNIPRO_VER_MASK = 0xF,
|
||||
};
|
||||
@@ -208,27 +236,27 @@ enum ufs_unipro_ver {
|
||||
/*
|
||||
* Data Link Layer Attributes
|
||||
*/
|
||||
#define DL_TXPREEMPTIONCAP 0x2000
|
||||
#define DL_TC0TXMAXSDUSIZE 0x2001
|
||||
#define DL_TC0RXINITCREDITVAL 0x2002
|
||||
#define DL_TC1TXMAXSDUSIZE 0x2003
|
||||
#define DL_TC1RXINITCREDITVAL 0x2004
|
||||
#define DL_TC0TXBUFFERSIZE 0x2005
|
||||
#define DL_TC1TXBUFFERSIZE 0x2006
|
||||
#define DL_TC0TXFCTHRESHOLD 0x2040
|
||||
#define DL_FC0PROTTIMEOUTVAL 0x2041
|
||||
#define DL_TC0REPLAYTIMEOUTVAL 0x2042
|
||||
#define DL_AFC0REQTIMEOUTVAL 0x2043
|
||||
#define DL_AFC0CREDITTHRESHOLD 0x2044
|
||||
#define DL_TC0OUTACKTHRESHOLD 0x2045
|
||||
#define DL_PEERTC0PRESENT 0x2046
|
||||
#define DL_PEERTC0RXINITCREVAL 0x2047
|
||||
#define DL_TC1TXFCTHRESHOLD 0x2060
|
||||
#define DL_FC1PROTTIMEOUTVAL 0x2061
|
||||
#define DL_TC1REPLAYTIMEOUTVAL 0x2062
|
||||
#define DL_AFC1REQTIMEOUTVAL 0x2063
|
||||
#define DL_AFC1CREDITTHRESHOLD 0x2064
|
||||
#define DL_TC1OUTACKTHRESHOLD 0x2065
|
||||
#define DL_TXPREEMPTIONCAP 0x2000
|
||||
#define DL_TC0TXMAXSDUSIZE 0x2001
|
||||
#define DL_TC0RXINITCREDITVAL 0x2002
|
||||
#define DL_TC0TXBUFFERSIZE 0x2005
|
||||
#define DL_PEERTC0PRESENT 0x2046
|
||||
#define DL_PEERTC0RXINITCREVAL 0x2047
|
||||
#define DL_TC1TXMAXSDUSIZE 0x2003
|
||||
#define DL_TC1RXINITCREDITVAL 0x2004
|
||||
#define DL_TC1TXBUFFERSIZE 0x2006
|
||||
#define DL_PEERTC1PRESENT 0x2066
|
||||
#define DL_PEERTC1RXINITCREVAL 0x2067
|
||||
|
||||
|
||||
Reference in New Issue
Block a user