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Merge tag 'xilinx-for-v2025.10-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Browse Source 
AMD/Xilinx/FPGA changes for v2025.10-rc1 v2

zynqmp:
- Generate fit-dtb.blob all the time
- Simplify power-domain driver bind

zynqmp_mini:
- Remove PSCI_RESET

fpga:
- Improve user feedback in case of FPGA bitstream load failure

misc:
- Fix kernel-doc in gpio zynq and axi_mrmac

spi:
- Revert fix in STIG mode

[trini: Remove CONFIG_FPGA_VERSALPL=y from sandbox due to
        sandbox+clang+asan test problem]
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2025-07-24 07:55:13 -06:00
parent 47b4a9b1a6 27fa1e2c17
commit 7bf2a52b49
27 changed files with 208 additions and 212 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/dts/zynqmp-binman-som.dts
View File

@@ -20,7 +20,6 @@
binman: binman {
multiple-images;
#ifdef CONFIG_SPL
fit-dtb.blob {
filename = "fit-dtb.blob";
pad-byte = <0>;
@@ -109,6 +108,7 @@
};
};
#ifdef CONFIG_SPL
/* Generation in a static way */
itb {
filename = U_BOOT_ITB_FILENAME;

101
cmd/fpga.c
View File

@@ -28,7 +28,7 @@ static long do_fpga_get_device(char *arg)
if (dev == FPGA_INVALID_DEVICE && arg)
dev = simple_strtol(arg, NULL, 16);
debug("%s: device = %ld\n", __func__, dev);
log_debug("device = %ld\n", dev);
return dev;
}
@@ -40,26 +40,26 @@ static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size,
size_t local_data_size;
long local_fpga_data;
debug("%s %d, %d\n", __func__, argc, cmdtp->maxargs);
log_debug("%d, %d\n", argc, cmdtp->maxargs);
if (argc != cmdtp->maxargs) {
debug("fpga: incorrect parameters passed\n");
return CMD_RET_USAGE;
log_err("Incorrect number of parameters passed\n");
return CMD_RET_FAILURE;
}
*dev = do_fpga_get_device(argv[0]);
local_fpga_data = simple_strtol(argv[1], NULL, 16);
if (!local_fpga_data) {
debug("fpga: zero fpga_data address\n");
return CMD_RET_USAGE;
log_err("Zero fpga_data address\n");
return CMD_RET_FAILURE;
}
*fpga_data = local_fpga_data;
local_data_size = hextoul(argv[2], NULL);
if (!local_data_size) {
debug("fpga: zero size\n");
return CMD_RET_USAGE;
log_err("Zero size\n");
return CMD_RET_FAILURE;
}
*data_size = local_data_size;
@@ -70,51 +70,52 @@ static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size,
static int do_fpga_loads(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
struct fpga_secure_info fpga_sec_info;
const int pos_userkey = 5;
size_t data_size = 0;
long fpga_data, dev;
int ret;
struct fpga_secure_info fpga_sec_info;
memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
if (argc < 5) {
debug("fpga: incorrect parameters passed\n");
return CMD_RET_USAGE;
if (argc < pos_userkey) {
log_err("Too few parameters passed\n");
return CMD_RET_FAILURE;
}
if (argc == 6)
if (argc == pos_userkey + 1)
fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
simple_strtoull(argv[5],
simple_strtoull(argv[pos_userkey],
NULL, 16);
else
/*
* If 6th parameter is not passed then do_fpga_check_params
* will get 5 instead of expected 6 which means that function
* return CMD_RET_USAGE. Increase number of params +1 to pass
* return CMD_RET_FAILURE. Increase number of params +1 to pass
* this.
*/
argc++;
ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
cmdtp, argc, argv);
if (ret)
return ret;
fpga_sec_info.encflag = (u8)hextoul(argv[4], NULL);
fpga_sec_info.authflag = (u8)hextoul(argv[3], NULL);
if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
debug("fpga: Use <fpga load> for NonSecure bitstream\n");
return CMD_RET_USAGE;
log_err("Use <fpga load> for NonSecure bitstream\n");
return CMD_RET_FAILURE;
}
if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
!fpga_sec_info.userkey_addr) {
debug("fpga: User key not provided\n");
return CMD_RET_USAGE;
log_err("User key not provided\n");
return CMD_RET_FAILURE;
}
ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
cmdtp, argc, argv);
if (ret)
return ret;
return fpga_loads(dev, (void *)fpga_data, data_size, &fpga_sec_info);
}
#endif
@@ -245,23 +246,23 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc,
ulong dev = do_fpga_get_device(argv[0]);
char *datastr = env_get("fpgadata");
debug("fpga: argc %x, dev %lx, datastr %s\n", argc, dev, datastr);
log_debug("argc %x, dev %lx, datastr %s\n", argc, dev, datastr);
if (dev == FPGA_INVALID_DEVICE) {
debug("fpga: Invalid fpga device\n");
return CMD_RET_USAGE;
log_err("Invalid fpga device\n");
return CMD_RET_FAILURE;
}
if (argc == 0 && !datastr) {
debug("fpga: No datastr passed\n");
return CMD_RET_USAGE;
log_err("No datastr passed\n");
return CMD_RET_FAILURE;
}
if (argc == 2) {
datastr = argv[1];
debug("fpga: Full command with two args\n");
log_debug("Full command with two args\n");
} else if (argc == 1 && !datastr) {
debug("fpga: Dev is setup - fpgadata passed\n");
log_debug("Dev is setup - fpgadata passed\n");
datastr = argv[0];
}
@@ -269,20 +270,20 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc,
if (fit_parse_subimage(datastr, (ulong)fpga_data,
&fit_addr, &fit_uname)) {
fpga_data = (void *)fit_addr;
debug("* fpga: subimage '%s' from FIT image ",
fit_uname);
debug("at 0x%08lx\n", fit_addr);
log_debug("* fpga: subimage '%s' from FIT image ",
fit_uname);
log_debug("at 0x%08lx\n", fit_addr);
} else
#endif
{
fpga_data = (void *)hextoul(datastr, NULL);
debug("* fpga: cmdline image address = 0x%08lx\n",
(ulong)fpga_data);
log_debug("* fpga: cmdline image address = 0x%08lx\n",
(ulong)fpga_data);
}
debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
log_debug("fpga_data = 0x%lx\n", (ulong)fpga_data);
if (!fpga_data) {
puts("Zero fpga_data address\n");
return CMD_RET_USAGE;
log_err("Zero fpga_data address\n");
return CMD_RET_FAILURE;
}
switch (genimg_get_format(fpga_data)) {
@@ -301,15 +302,15 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc,
data = image_get_load(hdr);
if (gunzip((void *)data, ~0UL, (void *)image_buf,
if (gunzip((void *)data, ~0U, (void *)image_buf,
&image_size) != 0) {
puts("GUNZIP: error\n");
log_err("Gunzip error\n");
return CMD_RET_FAILURE;
}
data_size = image_size;
#else
puts("Gunzip image is not supported\n");
return 1;
log_err("Gunzip image is not supported\n");
return CMD_RET_FAILURE;
#endif
} else {
data = (ulong)image_get_data(hdr);
@@ -327,12 +328,12 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc,
const void *fit_data;
if (!fit_uname) {
puts("No FIT subimage unit name\n");
log_err("No FIT subimage unit name\n");
return CMD_RET_FAILURE;
}
if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
puts("Bad FIT image format\n");
log_err("Bad FIT image format\n");
return CMD_RET_FAILURE;
}
@@ -348,7 +349,7 @@ static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc,
}
#endif
default:
puts("** Unknown image type\n");
log_err("Unknown image type\n");
return CMD_RET_FAILURE;
}
}
@@ -390,16 +391,16 @@ static int do_fpga_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
fpga_cmd = find_cmd_tbl(argv[1], fpga_commands,
ARRAY_SIZE(fpga_commands));
if (!fpga_cmd) {
debug("fpga: non existing command\n");
return CMD_RET_USAGE;
log_err("Non existing command\n");
return CMD_RET_FAILURE;
}
argc -= 2;
argv += 2;
if (argc > fpga_cmd->maxargs) {
debug("fpga: more parameters passed\n");
return CMD_RET_USAGE;
log_err("Too many parameters passed\n");
return CMD_RET_FAILURE;
}
ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv);

19
configs/sandbox_defconfig
View File

@@ -77,6 +77,11 @@ CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DEMO=y
CONFIG_CMD_FPGA_LOADP=y
CONFIG_CMD_FPGA_LOADBP=y
CONFIG_CMD_FPGA_LOADFS=y
CONFIG_CMD_FPGA_LOADMK=y
CONFIG_CMD_FPGA_LOAD_SECURE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPIO_READ=y
CONFIG_CMD_PWM=y
@@ -197,6 +202,20 @@ CONFIG_SANDBOX_DMA=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_ARM_FFA_TRANSPORT=y
CONFIG_FPGA_ALTERA=y
CONFIG_FPGA_STRATIX_II=y
CONFIG_FPGA_STRATIX_V=y
CONFIG_FPGA_ACEX1K=y
CONFIG_FPGA_CYCLON2=y
CONFIG_FPGA_LATTICE=y
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_SPARTAN2=y
CONFIG_FPGA_SPARTAN3=y
CONFIG_FPGA_VIRTEX2=y
CONFIG_SYS_FPGA_CHECK_BUSY=y
CONFIG_SYS_FPGA_CHECK_CTRLC=y
CONFIG_DM_FPGA=y
CONFIG_SANDBOX_FPGA=y
CONFIG_GPIO_HOG=y
CONFIG_DM_GPIO_LOOKUP_LABEL=y
CONFIG_QCOM_PMIC_GPIO=y

1
configs/xilinx_zynqmp_mini_defconfig
View File

@@ -11,6 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini"
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_XILINX_MINI=y
CONFIG_SYS_MEM_RSVD_FOR_MMU=y
# CONFIG_PSCI_RESET is not set
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
CONFIG_REMAKE_ELF=y

1
configs/xilinx_zynqmp_mini_emmc0_defconfig
View File

@@ -16,6 +16,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_SPL=y
CONFIG_XILINX_MINI=y
# CONFIG_PSCI_RESET is not set
CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
# CONFIG_EFI_LOADER is not set

1
configs/xilinx_zynqmp_mini_emmc1_defconfig
View File

@@ -16,6 +16,7 @@ CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_SPL=y
CONFIG_XILINX_MINI=y
# CONFIG_PSCI_RESET is not set
CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
# CONFIG_EFI_LOADER is not set

1
configs/xilinx_zynqmp_mini_nand_defconfig
View File

@@ -11,6 +11,7 @@ CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_XILINX_MINI=y
# CONFIG_PSCI_RESET is not set
CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
CONFIG_FIT=y

1
configs/xilinx_zynqmp_mini_nand_single_defconfig
View File

@@ -11,6 +11,7 @@ CONFIG_ENV_SIZE=0x80
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-mini-nand"
CONFIG_SYS_LOAD_ADDR=0x8000000
CONFIG_XILINX_MINI=y
# CONFIG_PSCI_RESET is not set
CONFIG_REMAKE_ELF=y
# CONFIG_MP is not set
CONFIG_FIT=y

7
drivers/firmware/firmware-zynqmp.c
View File

@@ -500,11 +500,8 @@ static int zynqmp_firmware_bind(struct udevice *dev)
if (!smc_call_handler)
return -EINVAL;
if ((IS_ENABLED(CONFIG_XPL_BUILD) &&
IS_ENABLED(CONFIG_SPL_POWER_DOMAIN) &&
IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) ||
(!IS_ENABLED(CONFIG_XPL_BUILD) &&
IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN))) {
if (CONFIG_IS_ENABLED(POWER_DOMAIN) &&
IS_ENABLED(CONFIG_ZYNQMP_POWER_DOMAIN)) {
ret = device_bind_driver_to_node(dev, "zynqmp_power_domain",
"zynqmp_power_domain",
dev_ofnode(dev), &child);

1
drivers/fpga/ACEX1K.c
View File

@@ -14,6 +14,7 @@
#include <log.h>
#include <ACEX1K.h> /* ACEX device family */
#include <linux/delay.h>
#include <time.h>
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).

1
drivers/fpga/Kconfig
View File

@@ -15,6 +15,7 @@ config FPGA_ALTERA
config FPGA_SOCFPGA
bool "Enable Gen5 and Arria10 common FPGA drivers"
depends on ARCH_SOCFPGA
select FPGA_ALTERA
help
Say Y here to enable the Gen5 and Arria10 common FPGA driver

103
drivers/fpga/fpga.c
View File

@@ -16,20 +16,6 @@
static int next_desc = FPGA_INVALID_DEVICE;
static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES];
/*
* fpga_no_sup
* 'no support' message function
*/
static void fpga_no_sup(char *fn, char *msg)
{
if (fn && msg)
printf("%s: No support for %s.\n", fn, msg);
else if (msg)
printf("No support for %s.\n", msg);
else
printf("No FPGA support!\n");
}
/* fpga_get_desc
* map a device number to a descriptor
*/
@@ -39,8 +25,8 @@ const fpga_desc *fpga_get_desc(int devnum)
if ((devnum >= 0) && (devnum < next_desc)) {
desc = &desc_table[devnum];
debug("%s: found fpga descriptor #%d @ 0x%p\n",
__func__, devnum, desc);
log_debug("found fpga descriptor #%d @ 0x%p\n",
devnum, desc);
}
return desc;
@@ -51,15 +37,15 @@ const fpga_desc *fpga_get_desc(int devnum)
* generic parameter checking code
*/
const fpga_desc *fpga_validate(int devnum, const void *buf,
size_t bsize, char *fn)
size_t bsize)
{
const fpga_desc *desc = fpga_get_desc(devnum);
if (!desc)
printf("%s: Invalid device number %d\n", fn, devnum);
log_err("Invalid device number %d\n", devnum);
if (!buf) {
printf("%s: Null buffer.\n", fn);
log_err("Null buffer.\n");
return NULL;
}
return desc;
@@ -75,40 +61,40 @@ static int fpga_dev_info(int devnum)
const fpga_desc *desc = fpga_get_desc(devnum);
if (desc) {
debug("%s: Device Descriptor @ 0x%p\n",
__func__, desc->devdesc);
log_info("Device Descriptor @ 0x%p\n",
desc->devdesc);
switch (desc->devtype) {
case fpga_xilinx:
#if defined(CONFIG_FPGA_XILINX)
printf("Xilinx Device\nDescriptor @ 0x%p\n", desc);
log_info("Xilinx Device\nDescriptor @ 0x%p\n", desc);
ret_val = xilinx_info(desc->devdesc);
#else
fpga_no_sup((char *)__func__, "Xilinx devices");
log_err("No support for Xilinx devices.\n");
#endif
break;
case fpga_altera:
#if defined(CONFIG_FPGA_ALTERA)
printf("Altera Device\nDescriptor @ 0x%p\n", desc);
log_info("Altera Device\nDescriptor @ 0x%p\n", desc);
ret_val = altera_info(desc->devdesc);
#else
fpga_no_sup((char *)__func__, "Altera devices");
log_err("No support for Altera devices.\n");
#endif
break;
case fpga_lattice:
#if defined(CONFIG_FPGA_LATTICE)
printf("Lattice Device\nDescriptor @ 0x%p\n", desc);
log_info("Lattice Device\nDescriptor @ 0x%p\n", desc);
ret_val = lattice_info(desc->devdesc);
#else
fpga_no_sup((char *)__func__, "Lattice devices");
log_err("No support for Lattice devices.\n");
#endif
break;
default:
printf("%s: Invalid or unsupported device type %d\n",
__func__, desc->devtype);
log_err("Invalid or unsupported device type %d\n",
desc->devtype);
}
} else {
printf("%s: Invalid device number %d\n", __func__, devnum);
log_err("Invalid device number %d\n", devnum);
}
return ret_val;
@@ -144,23 +130,22 @@ int fpga_add(fpga_type devtype, void *desc)
int devnum = FPGA_INVALID_DEVICE;
if (!desc) {
printf("%s: NULL device descriptor\n", __func__);
log_err("NULL device descriptor\n");
return devnum;
}
if (next_desc < 0) {
printf("%s: FPGA support not initialized!\n", __func__);
log_err("FPGA support not initialized!\n");
} else if ((devtype > fpga_min_type) && (devtype < fpga_undefined)) {
if (next_desc < CONFIG_MAX_FPGA_DEVICES) {
devnum = next_desc;
desc_table[next_desc].devtype = devtype;
desc_table[next_desc++].devdesc = desc;
} else {
printf("%s: Exceeded Max FPGA device count\n",
__func__);
log_err("Exceeded Max FPGA device count\n");
}
} else {
printf("%s: Unsupported FPGA type %d\n", __func__, devtype);
log_err("Unsupported FPGA type %d\n", devtype);
}
return devnum;
@@ -181,7 +166,7 @@ int __weak fpga_is_partial_data(int devnum, size_t img_len)
int __weak fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
bitstream_type bstype)
{
printf("Bitstream support not implemented for this FPGA device\n");
log_err("Bitstream support not implemented for this FPGA device\n");
return FPGA_FAIL;
}
@@ -190,8 +175,7 @@ int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo)
{
int ret_val = FPGA_FAIL; /* assume failure */
const fpga_desc *desc = fpga_validate(devnum, buf, size,
(char *)__func__);
const fpga_desc *desc = fpga_validate(devnum, buf, size);
if (desc) {
switch (desc->devtype) {
@@ -200,12 +184,12 @@ int fpga_fsload(int devnum, const void *buf, size_t size,
ret_val = xilinx_loadfs(desc->devdesc, buf, size,
fpga_fsinfo);
#else
fpga_no_sup((char *)__func__, "Xilinx devices");
log_err("No support for Xilinx devices.\n");
#endif
break;
default:
printf("%s: Invalid or unsupported device type %d\n",
__func__, desc->devtype);
log_err("Invalid or unsupported device type %d\n",
desc->devtype);
}
}
@@ -219,8 +203,7 @@ int fpga_loads(int devnum, const void *buf, size_t size,
{
int ret_val = FPGA_FAIL;
const fpga_desc *desc = fpga_validate(devnum, buf, size,
(char *)__func__);
const fpga_desc *desc = fpga_validate(devnum, buf, size);
if (desc) {
switch (desc->devtype) {
@@ -229,12 +212,12 @@ int fpga_loads(int devnum, const void *buf, size_t size,
ret_val = xilinx_loads(desc->devdesc, buf, size,
fpga_sec_info);
#else
fpga_no_sup((char *)__func__, "Xilinx devices");
log_err("No support for Xilinx devices.\n");
#endif
break;
default:
printf("%s: Invalid or unsupported device type %d\n",
__func__, desc->devtype);
log_err("Invalid or unsupported device type %d\n",
desc->devtype);
}
}
@@ -265,8 +248,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype,
{
int ret_val = FPGA_FAIL; /* assume failure */
int ret_notify;
const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
(char *)__func__);
const fpga_desc *desc = fpga_validate(devnum, buf, bsize);
if (desc) {
switch (desc->devtype) {
@@ -275,26 +257,26 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype,
ret_val = xilinx_load(desc->devdesc, buf, bsize,
bstype, flags);
#else
fpga_no_sup((char *)__func__, "Xilinx devices");
log_err("No support for Xilinx devices.\n");
#endif
break;
case fpga_altera:
#if defined(CONFIG_FPGA_ALTERA)
ret_val = altera_load(desc->devdesc, buf, bsize);
#else
fpga_no_sup((char *)__func__, "Altera devices");
log_err("No support for Altera devices.\n");
#endif
break;
case fpga_lattice:
#if defined(CONFIG_FPGA_LATTICE)
ret_val = lattice_load(desc->devdesc, buf, bsize);
#else
fpga_no_sup((char *)__func__, "Lattice devices");
log_err("No support for Lattice devices.\n");
#endif
break;
default:
printf("%s: Invalid or unsupported device type %d\n",
__func__, desc->devtype);
log_err("Invalid or unsupported device type %d\n",
desc->devtype);
}
}
@@ -312,8 +294,7 @@ int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype,
int fpga_dump(int devnum, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL; /* assume failure */
const fpga_desc *desc = fpga_validate(devnum, buf, bsize,
(char *)__func__);
const fpga_desc *desc = fpga_validate(devnum, buf, bsize);
if (desc) {
switch (desc->devtype) {
@@ -321,26 +302,26 @@ int fpga_dump(int devnum, const void *buf, size_t bsize)
#if defined(CONFIG_FPGA_XILINX)
ret_val = xilinx_dump(desc->devdesc, buf, bsize);
#else
fpga_no_sup((char *)__func__, "Xilinx devices");
log_err("No support for Xilinx devices.\n");
#endif
break;
case fpga_altera:
#if defined(CONFIG_FPGA_ALTERA)
ret_val = altera_dump(desc->devdesc, buf, bsize);
#else
fpga_no_sup((char *)__func__, "Altera devices");
log_err("No support for Altera devices.\n");
#endif
break;
case fpga_lattice:
#if defined(CONFIG_FPGA_LATTICE)
ret_val = lattice_dump(desc->devdesc, buf, bsize);
#else
fpga_no_sup((char *)__func__, "Lattice devices");
log_err("No support for Lattice devices.\n");
#endif
break;
default:
printf("%s: Invalid or unsupported device type %d\n",
__func__, desc->devtype);
log_err("Invalid or unsupported device type %d\n",
desc->devtype);
}
}
@@ -363,7 +344,7 @@ int fpga_info(int devnum)
return FPGA_SUCCESS;
} else {
printf("%s: No FPGA devices available.\n", __func__);
log_err("No FPGA devices available.\n");
return FPGA_FAIL;
}
}

13
drivers/fpga/ivm_core.c
View File

@@ -33,6 +33,7 @@
#include <linux/string.h>
#include <malloc.h>
#include <lattice.h>
#include <vsprintf.h>
#define vme_out_char(c) printf("%c", c)
#define vme_out_hex(c) printf("%x", c)
@@ -291,7 +292,7 @@ unsigned short g_usLVDSPairCount;
*/
static signed char ispVMDataCode(void);
static long int ispVMDataSize(void);
static long ispVMDataSize(void);
static void ispVMData(unsigned char *Data);
static signed char ispVMShift(signed char Code);
static signed char ispVMAmble(signed char Code);
@@ -589,7 +590,7 @@ void ispVMFreeMem(void)
*
*/
long int ispVMDataSize()
long ispVMDataSize(void)
{
/* 09/11/07 NN added local variables initialization */
long int iSize = 0;
@@ -614,7 +615,7 @@ long int ispVMDataSize()
*
*/
signed char ispVMCode()
signed char ispVMCode(void)
{
/* 09/11/07 NN added local variables initialization */
unsigned short iRepeatSize = 0;
@@ -1113,7 +1114,7 @@ signed char ispVMCode()
*
*/
signed char ispVMDataCode()
signed char ispVMDataCode(void)
{
/* 09/11/07 NN added local variables initialization */
signed char cDataByte = 0;
@@ -2475,7 +2476,7 @@ void ispVMStateMachine(signed char cNextJTAGState)
*
*/
void ispVMStart()
void ispVMStart(void)
{
#ifdef DEBUG
printf("// ISPVM EMBEDDED ADDED\n");
@@ -2504,7 +2505,7 @@ void ispVMStart()
*
*/
void ispVMEnd()
void ispVMEnd(void)
{
#ifdef DEBUG
printf("// ISPVM EMBEDDED ADDED\n");

4
drivers/fpga/lattice.c
View File

@@ -350,8 +350,8 @@ int lattice_info(Lattice_desc *desc)
printf("Unsupported interface type, %d\n", desc->iface);
}
printf("Device Size: \t%d bytes\n",
desc->size);
printf("Device Size: \t%zu bytes\n",
desc->size);
if (desc->iface_fns) {
printf("Device Function Table @ 0x%p\n",

1
drivers/fpga/spartan2.c
View File

@@ -9,6 +9,7 @@
#include <config.h> /* core U-Boot definitions */
#include <log.h>
#include <spartan2.h> /* Spartan-II device family */
#include <time.h>
/* Note: The assumption is that we cannot possibly run fast enough to
* overrun the device (the Slave Parallel mode can free run at 50MHz).

132
drivers/fpga/stratixII.c
View File

@@ -5,92 +5,41 @@
*/
#include <altera.h>
#include <stratixII.h>
#include <linux/delay.h>
int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
int isSerial, int isSecure);
int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize);
/****************************************************************/
/* Stratix II Generic Implementation */
int StratixII_load (Altera_desc * desc, void *buf, size_t bsize)
int StratixII_ps_fpp_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case passive_serial:
ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 1, 0);
break;
case fast_passive_parallel:
ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 0);
break;
case fast_passive_parallel_security:
ret_val = StratixII_ps_fpp_load (desc, buf, bsize, 0, 1);
break;
/* Add new interface types here */
default:
printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
desc->iface);
}
return ret_val;
}
int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case passive_serial:
case fast_passive_parallel:
case fast_passive_parallel_security:
ret_val = StratixII_ps_fpp_dump (desc, buf, bsize);
break;
/* Add new interface types here */
default:
printf ("%s: Unsupported interface type, %d\n", __FUNCTION__,
desc->iface);
}
return ret_val;
}
int StratixII_info (Altera_desc * desc)
{
return FPGA_SUCCESS;
}
int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize)
{
printf ("Stratix II Fast Passive Parallel dump is not implemented\n");
printf("Stratix II Fast Passive Parallel dump is not implemented\n");
return FPGA_FAIL;
}
int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
int isSerial, int isSecure)
int StratixII_ps_fpp_load(Altera_desc *desc, const void *buf, size_t bsize,
int isSerial, int isSecure)
{
altera_board_specific_func *fns;
int cookie;
int ret_val = FPGA_FAIL;
int bytecount;
char *buff = buf;
const char *buff = buf;
int i;
if (!desc) {
printf ("%s(%d) Altera_desc missing\n", __FUNCTION__, __LINE__);
log_err("Altera_desc missing\n");
return FPGA_FAIL;
}
if (!buff) {
printf ("%s(%d) buffer is missing\n", __FUNCTION__, __LINE__);
log_err("buffer is missing\n");
return FPGA_FAIL;
}
if (!bsize) {
printf ("%s(%d) size is zero\n", __FUNCTION__, __LINE__);
log_err("size is zero\n");
return FPGA_FAIL;
}
if (!desc->iface_fns) {
printf
("%s(%d) Altera_desc function interface table is missing\n",
__FUNCTION__, __LINE__);
log_err("Altera_desc function interface table is missing\n");
return FPGA_FAIL;
}
fns = (altera_board_specific_func *) (desc->iface_fns);
@@ -99,9 +48,7 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
if (!
(fns->config && fns->status && fns->done && fns->data
&& fns->abort)) {
printf
("%s(%d) Missing some function in the function interface table\n",
__FUNCTION__, __LINE__);
log_err("Missing some function in the function interface table\n");
return FPGA_FAIL;
}
@@ -124,13 +71,12 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
bytecount = 0;
fns->clk (0, 1, cookie);
printf ("loading to fpga ");
printf("loading to fpga ");
while (bytecount < bsize) {
/* 3.1 check stratix has not signaled us an error */
if (fns->status (cookie) != 1) {
printf
("\n%s(%d) Stratix failed (byte transferred till failure 0x%x)\n",
__FUNCTION__, __LINE__, bytecount);
log_err("\nStratix failed (byte transferred till failure 0x%x)\n",
bytecount);
fns->abort (cookie);
return FPGA_FAIL;
}
@@ -162,7 +108,7 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
/* 3.5 while clk is deasserted it is safe to print some progress indication */
if ((bytecount % (bsize / 100)) == 0) {
printf ("\b\b\b%02d\%", bytecount * 100 / bsize);
printf("\b\b\b%02zu\%%", bytecount * 100 / bsize);
}
}
@@ -170,11 +116,11 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
fns->clk (1, 1, cookie);
udelay(100);
if (!fns->done (cookie)) {
printf (" error!.\n");
printf(" error!.\n");
fns->abort (cookie);
return FPGA_FAIL;
} else {
printf ("\b\b\b done.\n");
printf("\b\b\b done.\n");
}
/* 5. call lower layer post configuration */
@@ -187,3 +133,47 @@ int StratixII_ps_fpp_load (Altera_desc * desc, void *buf, size_t bsize,
return FPGA_SUCCESS;
}
int StratixII_load(Altera_desc *desc, const void *buf, size_t size)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case passive_serial:
ret_val = StratixII_ps_fpp_load(desc, buf, size, 1, 0);
break;
case fast_passive_parallel:
ret_val = StratixII_ps_fpp_load(desc, buf, size, 0, 0);
break;
case fast_passive_parallel_security:
ret_val = StratixII_ps_fpp_load(desc, buf, size, 0, 1);
break;
/* Add new interface types here */
default:
log_err("Unsupported interface type, %d\n", desc->iface);
}
return ret_val;
}
int StratixII_dump(Altera_desc *desc, const void *buf, size_t bsize)
{
int ret_val = FPGA_FAIL;
switch (desc->iface) {
case passive_serial:
case fast_passive_parallel:
case fast_passive_parallel_security:
ret_val = StratixII_ps_fpp_dump(desc, buf, bsize);
break;
/* Add new interface types here */
default:
log_err("Unsupported interface type, %d\n", desc->iface);
}
return ret_val;
}
int StratixII_info(Altera_desc *desc)
{
return FPGA_SUCCESS;
}

2
drivers/fpga/stratixv.c
View File

@@ -48,7 +48,7 @@ int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
int spi_dev;
int ret = 0;
if ((u32)rbf_data & 0x3) {
if ((size_t)rbf_data & 0x3) {
puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
return -EINVAL;
}

1
drivers/fpga/versalpl.c
View File

@@ -6,7 +6,6 @@
#include <cpu_func.h>
#include <log.h>
#include <asm/arch/sys_proto.h>
#include <memalign.h>
#include <versalpl.h>
#include <zynqmp_firmware.h>

2
drivers/fpga/virtex2.c
View File

@@ -19,6 +19,7 @@
#include <log.h>
#include <virtex2.h>
#include <linux/delay.h>
#include <time.h>
/*
* If the SelectMap interface can be overrun by the processor, enable
@@ -301,6 +302,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
size_t bytecount = 0;
unsigned char *data = (unsigned char *)buf;
int cookie = desc->cookie;
unsigned long ts;
ret_val = virtex2_slave_pre(fn, cookie);
if (ret_val != FPGA_SUCCESS)

2
drivers/fpga/xilinx.c
View File

@@ -49,7 +49,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
dataptr = (unsigned char *)fpgadata;
/* Find out fpga_description */
desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
desc = fpga_validate(devnum, dataptr, 0);
/* Assign xilinx device description */
xdesc = desc->devdesc;

4
drivers/fpga/zynqmppl.c
View File

@@ -191,8 +191,8 @@ static int zynqmp_validate_bitstream(xilinx_desc *desc, const void *buf,
}
if ((ulong)buf < SZ_1M) {
printf("%s: Bitstream has to be placed up to 1MB (%px)\n",
__func__, buf);
log_err("Bitstream has to be placed above 1MB (%px)\n",
buf);
return FPGA_FAIL;
}

4
drivers/fpga/zynqpl.c
View File

@@ -360,8 +360,8 @@ static int zynq_validate_bitstream(xilinx_desc *desc, const void *buf,
}
if ((u32)buf < SZ_1M) {
printf("%s: Bitstream has to be placed up to 1MB (%x)\n",
__func__, (u32)buf);
log_err("Bitstream has to be placed above 1MB (%x)\n",
(u32)buf);
return FPGA_FAIL;
}

1
drivers/gpio/zynq_gpio.c
View File

@@ -184,6 +184,7 @@ static const struct zynq_platform_data zynq_gpio_def = {
* pin
* @bank_pin_num: an output parameter used to return pin number within a bank
* for the given gpio pin
* @dev: Pointer to our device structure.
*
* Returns the bank number and pin offset within the bank.
*/

4
drivers/net/xilinx_axi_mrmac.c
View File

@@ -346,7 +346,7 @@ static bool isrxready(struct axi_mrmac_priv *priv)
* axi_mrmac_recv - MRMAC Rx function
* @dev: udevice structure
* @flags: flags from network stack
* @packetp pointer to received data
* @packetp: pointer to received data
*
* Return: received data length on success, negative value on errors
*
@@ -399,7 +399,7 @@ static int axi_mrmac_recv(struct udevice *dev, int flags, uchar **packetp)
* axi_mrmac_free_pkt - MRMAC free packet function
* @dev: udevice structure
* @packet: receive buffer pointer
* @length received data length
* @length: received data length
*
* Return: 0 on success, negative value on errors
*

3
drivers/spi/cadence_qspi_apb.c
View File

@@ -558,9 +558,6 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv,
void *reg_base = priv->regbase;
u8 opcode;
if (priv->dtr)
txlen += txlen & 1;
if (priv->dtr)
opcode = op->cmd.opcode >> 8;
else

2
include/fpga.h
View File

@@ -79,7 +79,7 @@ int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
int fpga_dump(int devnum, const void *buf, size_t bsize);
int fpga_info(int devnum);
const fpga_desc *fpga_validate(int devnum, const void *buf,
size_t bsize, char *fn);
size_t bsize);
int fpga_compatible2flag(int devnum, const char *compatible);
#endif /* _FPGA_H_ */

6
include/stratixII.h
View File

@@ -6,8 +6,8 @@
#ifndef _STRATIXII_H_
#define _STRATIXII_H_
extern int StratixII_load (Altera_desc * desc, void *image, size_t size);
extern int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize);
extern int StratixII_info (Altera_desc * desc);
int StratixII_load(Altera_desc *desc, const void *buf, size_t size);
int StratixII_dump(Altera_desc *desc, const void *buf, size_t bsize);
int StratixII_info(Altera_desc *desc);
#endif /* _STRATIXII_H_ */