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clk: mediatek: add separate gates_offs for cg gates

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Add a gates_offs field to struct mtk_cg_priv and use that instead of
struct mtk_clk_tree.gates_offs.

Prior to this change, struct mtk_clk_tree.gates_offs could be the offset
of struct mtk_clk_tree.gates or struct mtk_cg_priv.gates depending on
the context. This was confusing and error-prone. For example, in mt8365
there is one set of gates that needs an offset and one that does not
that share the same struct mtk_clk_tree. This is fixed in this patch by
giving the correct offset for each gate separately.

Signed-off-by: David Lechner <dlechner@baylibre.com>
This commit is contained in:
David Lechner
2026-01-07 10:21:09 -06:00
committed by Tom Rini
parent 32087f61ad
commit a694df199a
15 changed files with 52 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/clk/mediatek/clk-mt7622.c
View File

@@ -693,7 +693,7 @@ static int mt7622_pericfg_probe(struct udevice *dev)
static int mt7622_pciesys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs,
ARRAY_SIZE(pcie_cgs));
ARRAY_SIZE(pcie_cgs), 0);
}
static int mt7622_pciesys_bind(struct udevice *dev)
@@ -712,7 +712,7 @@ static int mt7622_pciesys_bind(struct udevice *dev)
static int mt7622_ethsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs,
ARRAY_SIZE(eth_cgs));
ARRAY_SIZE(eth_cgs), 0);
}
static int mt7622_ethsys_bind(struct udevice *dev)
@@ -731,13 +731,13 @@ static int mt7622_ethsys_bind(struct udevice *dev)
static int mt7622_sgmiisys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs,
ARRAY_SIZE(sgmii_cgs));
ARRAY_SIZE(sgmii_cgs), 0);
}
static int mt7622_ssusbsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, ssusb_cgs,
ARRAY_SIZE(ssusb_cgs));
ARRAY_SIZE(ssusb_cgs), 0);
}
static const struct udevice_id mt7622_apmixed_compat[] = {

8
drivers/clk/mediatek/clk-mt7623.c
View File

@@ -1055,15 +1055,13 @@ static int mt7623_topckgen_probe(struct udevice *dev)
}
static const struct mtk_clk_tree mt7623_clk_gate_tree = {
/* Each CLK ID for gates clock starts at index 1 */
.gates_offs = 1,
.xtal_rate = 26 * MHZ,
};
static int mt7623_infracfg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, infra_cgs,
ARRAY_SIZE(infra_cgs));
ARRAY_SIZE(infra_cgs), 1);
}
static const struct mtk_clk_tree mt7623_clk_peri_tree = {
@@ -1086,13 +1084,13 @@ static int mt7623_pericfg_probe(struct udevice *dev)
static int mt7623_hifsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, hif_cgs,
ARRAY_SIZE(hif_cgs));
ARRAY_SIZE(hif_cgs), 1);
}
static int mt7623_ethsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7623_clk_gate_tree, eth_cgs,
ARRAY_SIZE(eth_cgs));
ARRAY_SIZE(eth_cgs), 1);
}
static int mt7623_ethsys_hifsys_bind(struct udevice *dev)

11
drivers/clk/mediatek/clk-mt7629.c
View File

@@ -581,7 +581,6 @@ static const struct mtk_clk_tree mt7629_clk_tree = {
static const struct mtk_clk_tree mt7629_peri_clk_tree = {
.xtal_rate = 40 * MHZ,
.xtal2_rate = 20 * MHZ,
.gates_offs = CLK_PERI_PWM1_PD,
.fdivs_offs = CLK_TOP_TO_USB3_SYS,
.muxes_offs = CLK_TOP_AXI_SEL,
.plls = apmixed_plls,
@@ -635,19 +634,19 @@ static int mt7629_topckgen_probe(struct udevice *dev)
static int mt7629_infracfg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, infra_cgs,
ARRAY_SIZE(infra_cgs));
ARRAY_SIZE(infra_cgs), 0);
}
static int mt7629_pericfg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7629_peri_clk_tree, peri_cgs,
ARRAY_SIZE(peri_cgs));
ARRAY_SIZE(peri_cgs), CLK_PERI_PWM1_PD);
}
static int mt7629_ethsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, eth_cgs,
ARRAY_SIZE(eth_cgs));
ARRAY_SIZE(eth_cgs), 0);
}
static int mt7629_ethsys_bind(struct udevice *dev)
@@ -666,13 +665,13 @@ static int mt7629_ethsys_bind(struct udevice *dev)
static int mt7629_sgmiisys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, sgmii_cgs,
ARRAY_SIZE(sgmii_cgs));
ARRAY_SIZE(sgmii_cgs), 0);
}
static int mt7629_ssusbsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, ssusb_cgs,
ARRAY_SIZE(ssusb_cgs));
ARRAY_SIZE(ssusb_cgs), 0);
}
static const struct udevice_id mt7629_apmixed_compat[] = {

6
drivers/clk/mediatek/clk-mt7981.c
View File

@@ -631,7 +631,7 @@ static const struct mtk_gate sgmii0_cgs[] = {
static int mt7981_sgmii0sys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,
sgmii0_cgs, ARRAY_SIZE(sgmii0_cgs));
sgmii0_cgs, ARRAY_SIZE(sgmii0_cgs), 0);
}
static const struct udevice_id mt7981_sgmii0sys_compat[] = {
@@ -658,7 +658,7 @@ static const struct mtk_gate sgmii1_cgs[] = {
static int mt7981_sgmii1sys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,
sgmii1_cgs, ARRAY_SIZE(sgmii1_cgs));
sgmii1_cgs, ARRAY_SIZE(sgmii1_cgs), 0);
}
static const struct udevice_id mt7981_sgmii1sys_compat[] = {
@@ -699,7 +699,7 @@ static const struct mtk_gate eth_cgs[] = {
static int mt7981_ethsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,
eth_cgs, ARRAY_SIZE(eth_cgs));
eth_cgs, ARRAY_SIZE(eth_cgs), 0);
}
static int mt7981_ethsys_bind(struct udevice *dev)

2
drivers/clk/mediatek/clk-mt7986.c
View File

@@ -637,7 +637,7 @@ static const struct mtk_gate eth_cgs[] = {
static int mt7986_ethsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7986_topckgen_clk_tree, eth_cgs,
ARRAY_SIZE(eth_cgs));
ARRAY_SIZE(eth_cgs), 0);
}
static int mt7986_ethsys_bind(struct udevice *dev)

2
drivers/clk/mediatek/clk-mt7987.c
View File

@@ -819,7 +819,7 @@ static const struct mtk_gate eth_cgs[] = {
static int mt7987_ethsys_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7987_topckgen_clk_tree, eth_cgs,
ARRAY_SIZE(eth_cgs));
ARRAY_SIZE(eth_cgs), 0);
}
static int mt7987_ethsys_bind(struct udevice *dev)

8
drivers/clk/mediatek/clk-mt7988.c
View File

@@ -893,7 +893,7 @@ static int mt7988_ethdma_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
ethdma_mtk_gate,
ARRAY_SIZE(ethdma_mtk_gate));
ARRAY_SIZE(ethdma_mtk_gate), 0);
}
static int mt7988_ethdma_bind(struct udevice *dev)
@@ -952,7 +952,7 @@ static int mt7988_sgmiisys_0_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
sgmiisys_0_mtk_gate,
ARRAY_SIZE(sgmiisys_0_mtk_gate));
ARRAY_SIZE(sgmiisys_0_mtk_gate), 0);
}
static const struct udevice_id mt7988_sgmiisys_0_compat[] = {
@@ -997,7 +997,7 @@ static int mt7988_sgmiisys_1_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
sgmiisys_1_mtk_gate,
ARRAY_SIZE(sgmiisys_1_mtk_gate));
ARRAY_SIZE(sgmiisys_1_mtk_gate), 0);
}
static const struct udevice_id mt7988_sgmiisys_1_compat[] = {
@@ -1044,7 +1044,7 @@ static int mt7988_ethwarp_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
ethwarp_mtk_gate,
ARRAY_SIZE(ethwarp_mtk_gate));
ARRAY_SIZE(ethwarp_mtk_gate), 0);
}
static int mt7988_ethwarp_bind(struct udevice *dev)

2
drivers/clk/mediatek/clk-mt8183.c
View File

@@ -778,7 +778,7 @@ static int mt8183_topckgen_probe(struct udevice *dev)
static int mt8183_infracfg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt8183_clk_tree, infra_clks,
ARRAY_SIZE(infra_clks));
ARRAY_SIZE(infra_clks), 0);
}
static const struct udevice_id mt8183_apmixed_compat[] = {

22
drivers/clk/mediatek/clk-mt8188.c
View File

@@ -1535,7 +1535,6 @@ static const struct mtk_gate infracfg_ao_clks[] = {
static const struct mtk_clk_tree mt8188_infracfg_ao_clk_tree = {
.xtal_rate = 26 * MHZ,
.xtal2_rate = 26 * MHZ,
.gates_offs = 0, /* CLK_INFRA_AO_PMIC_TMR */
};
static const struct mtk_gate_regs peri_ao_cg_regs = {
@@ -1570,7 +1569,6 @@ static const struct mtk_gate pericfg_ao_clks[] = {
static const struct mtk_clk_tree mt8188_pericfg_ao_clk_tree = {
.xtal_rate = 26 * MHZ,
.xtal2_rate = 26 * MHZ,
.gates_offs = 0, /* CLK_PERI_AO_ETHERNET */
};
static const struct mtk_gate_regs top0_cg_regs = {
@@ -1629,7 +1627,6 @@ static const struct mtk_gate topckgen_cg_clks[] = {
static const struct mtk_clk_tree mt8188_topckgen_cg_clk_tree = {
.xtal_rate = 26 * MHZ,
.xtal2_rate = 26 * MHZ,
.gates_offs = 185, /* CLK_TOP_CFGREG_CLOCK_EN_VPP0 */
};
static const struct mtk_gate_regs imp_iic_wrap_cg_regs = {
@@ -1665,22 +1662,16 @@ static const struct mtk_gate imp_iic_wrap_en_clks[] = {
const struct mtk_clk_tree mt8188_imp_iic_wrap_c_clk_tree = {
.xtal_rate = 26 * MHZ,
.xtal2_rate = 26 * MHZ,
/* CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0 */
.gates_offs = 0,
};
const struct mtk_clk_tree mt8188_imp_iic_wrap_w_clk_tree = {
.xtal_rate = 26 * MHZ,
.xtal2_rate = 26 * MHZ,
/* CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C1 */
.gates_offs = 0,
};
const struct mtk_clk_tree mt8188_imp_iic_wrap_en_clk_tree = {
.xtal_rate = 26 * MHZ,
.xtal2_rate = 26 * MHZ,
/* imp_iic_wrap_en: CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5 */
.gates_offs = 0,
};
static int mt8188_apmixedsys_probe(struct udevice *dev)
@@ -1697,42 +1688,43 @@ static int mt8188_topckgen_cg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt8188_topckgen_cg_clk_tree,
topckgen_cg_clks,
ARRAY_SIZE(topckgen_cg_clks));
ARRAY_SIZE(topckgen_cg_clks),
CLK_TOP_CFGREG_CLOCK_EN_VPP0);
}
static int mt8188_infracfg_ao_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt8188_infracfg_ao_clk_tree,
infracfg_ao_clks,
ARRAY_SIZE(infracfg_ao_clks));
ARRAY_SIZE(infracfg_ao_clks), 0);
}
static int mt8188_pericfg_ao_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt8188_pericfg_ao_clk_tree,
pericfg_ao_clks,
ARRAY_SIZE(pericfg_ao_clks));
ARRAY_SIZE(pericfg_ao_clks), 0);
}
static int mt8188_imp_iic_wrap_c_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt8188_imp_iic_wrap_c_clk_tree,
imp_iic_wrap_c_clks,
ARRAY_SIZE(imp_iic_wrap_c_clks));
ARRAY_SIZE(imp_iic_wrap_c_clks), 0);
}
static int mt8188_imp_iic_wrap_w_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt8188_imp_iic_wrap_w_clk_tree,
imp_iic_wrap_w_clks,
ARRAY_SIZE(imp_iic_wrap_w_clks));
ARRAY_SIZE(imp_iic_wrap_w_clks), 0);
}
static int mt8188_imp_iic_wrap_en_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt8188_imp_iic_wrap_en_clk_tree,
imp_iic_wrap_en_clks,
ARRAY_SIZE(imp_iic_wrap_en_clks));
ARRAY_SIZE(imp_iic_wrap_en_clks), 0);
}
static const struct udevice_id mt8188_apmixed_compat[] = {

5
drivers/clk/mediatek/clk-mt8365.c
View File

@@ -708,13 +708,14 @@ static int mt8365_topckgen_probe(struct udevice *dev)
static int mt8365_topckgen_cg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt8365_clk_tree, top_clk_gates,
ARRAY_SIZE(top_clk_gates));
ARRAY_SIZE(top_clk_gates),
CLK_TOP_AUD_I2S0_M);
}
static int mt8365_infracfg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt8365_clk_tree, ifr_clks,
ARRAY_SIZE(ifr_clks));
ARRAY_SIZE(ifr_clks), 0);
}
static const struct udevice_id mt8365_apmixed_compat[] = {

4
drivers/clk/mediatek/clk-mt8512.c
View File

@@ -809,13 +809,13 @@ static int mt8512_topckgen_probe(struct udevice *dev)
static int mt8512_topckgen_cg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, top_clks,
ARRAY_SIZE(top_clks));
ARRAY_SIZE(top_clks), 0);
}
static int mt8512_infracfg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt8512_clk_tree, infra_clks,
ARRAY_SIZE(infra_clks));
ARRAY_SIZE(infra_clks), 0);
}
static const struct udevice_id mt8512_apmixed_compat[] = {

2
drivers/clk/mediatek/clk-mt8516.c
View File

@@ -758,7 +758,7 @@ static int mt8516_topckgen_probe(struct udevice *dev)
static int mt8516_topckgen_cg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt8516_clk_tree, top_clks,
ARRAY_SIZE(top_clks));
ARRAY_SIZE(top_clks), 0);
}
static const struct udevice_id mt8516_apmixed_compat[] = {

2
drivers/clk/mediatek/clk-mt8518.c
View File

@@ -1514,7 +1514,7 @@ static int mt8518_topckgen_probe(struct udevice *dev)
static int mt8518_topckgen_cg_probe(struct udevice *dev)
{
return mtk_common_clk_gate_init(dev, &mt8518_clk_tree, top_clks,
ARRAY_SIZE(top_clks));
ARRAY_SIZE(top_clks), 0);
}
static const struct udevice_id mt8518_apmixed_compat[] = {

24
drivers/clk/mediatek/clk-mtk.c
View File

@@ -1018,8 +1018,8 @@ static const int mtk_clk_gate_of_xlate(struct clk *clk,
if (ret)
return ret;
if (clk->id >= tree->gates_offs &&
clk->id < tree->gates_offs + priv->num_gates)
if (clk->id >= priv->gates_offs &&
clk->id < priv->gates_offs + priv->num_gates)
return 0;
return -ENOENT;
@@ -1030,10 +1030,10 @@ static int mtk_clk_gate_enable(struct clk *clk)
struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
const struct mtk_gate *gate;
if (clk->id < priv->tree->gates_offs)
if (clk->id < priv->gates_offs)
return -EINVAL;
gate = &priv->gates[clk->id - priv->tree->gates_offs];
gate = &priv->gates[clk->id - priv->gates_offs];
return mtk_gate_enable(priv->base, gate);
}
@@ -1042,10 +1042,10 @@ static int mtk_clk_gate_disable(struct clk *clk)
struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
const struct mtk_gate *gate;
if (clk->id < priv->tree->gates_offs)
if (clk->id < priv->gates_offs)
return -EINVAL;
gate = &priv->gates[clk->id - priv->tree->gates_offs];
gate = &priv->gates[clk->id - priv->gates_offs];
return mtk_gate_disable(priv->base, gate);
}
@@ -1055,10 +1055,10 @@ static ulong mtk_clk_gate_get_rate(struct clk *clk)
struct udevice *parent = priv->parent;
const struct mtk_gate *gate;
if (clk->id < priv->tree->gates_offs)
if (clk->id < priv->gates_offs)
return -EINVAL;
gate = &priv->gates[clk->id - priv->tree->gates_offs];
gate = &priv->gates[clk->id - priv->gates_offs];
/*
* With requesting a TOPCKGEN parent, make sure the dev parent
* is actually topckgen. This might not be the case for an
@@ -1094,8 +1094,8 @@ static void mtk_clk_gate_dump(struct udevice *dev)
const struct mtk_gate *gate = &priv->gates[i];
printf("[GATE%u] DT: %u", i, gate->id);
mtk_clk_print_mapped_id(gate->id, i + tree->gates_offs, tree->id_offs_map);
mtk_clk_print_rate(dev, i + tree->gates_offs);
mtk_clk_print_mapped_id(gate->id, i + priv->gates_offs, tree->id_offs_map);
mtk_clk_print_rate(dev, i + priv->gates_offs);
mtk_clk_print_single_parent(gate->parent, gate->flags);
printf("\n");
}
@@ -1196,7 +1196,8 @@ int mtk_common_clk_infrasys_init(struct udevice *dev,
int mtk_common_clk_gate_init(struct udevice *dev,
const struct mtk_clk_tree *tree,
const struct mtk_gate *gates, int num_gates)
const struct mtk_gate *gates, int num_gates,
int gates_offs)
{
struct mtk_cg_priv *priv = dev_get_priv(dev);
struct udevice *parent;
@@ -1218,6 +1219,7 @@ int mtk_common_clk_gate_init(struct udevice *dev,
priv->tree = tree;
priv->gates = gates;
priv->num_gates = num_gates;
priv->gates_offs = gates_offs;
return 0;
}

4
drivers/clk/mediatek/clk-mtk.h
View File

@@ -285,6 +285,7 @@ struct mtk_cg_priv {
const struct mtk_clk_tree *tree;
const struct mtk_gate *gates;
int num_gates;
int gates_offs;
};
extern const struct clk_ops mtk_clk_apmixedsys_ops;
@@ -299,6 +300,7 @@ int mtk_common_clk_infrasys_init(struct udevice *dev,
const struct mtk_clk_tree *tree);
int mtk_common_clk_gate_init(struct udevice *dev,
const struct mtk_clk_tree *tree,
const struct mtk_gate *gates, int num_gates);
const struct mtk_gate *gates, int num_gates,
int gates_offs);
#endif /* __DRV_CLK_MTK_H */