arm64: versal-net: Add PL bit stream load support
Add support for loading the secure & non-secure pdi images and PL bitstream on the Versal NET platform. The FPGA driver is enabled to load the bitstream in PDI format on the AMD Versal NET device. PDI is the new programmable device image format for Versal NET, and the bitstream for the Versal NET platform is generated exclusively in this format. The source code for the versalnet loadpdi command and the CONFIG_CMD_VERSAL_NET configuration has been removed. It now utilizes the fpga load <dev> <address> <length> command to load secure & non-secure pdi images. Signed-off-by: Prasad Kummari <prasad.kummari@amd.com> Link: https://lore.kernel.org/r/20250327105200.1262615-2-prasad.kummari@amd.com Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Prasad Kummari
committed by
Michal Simek
Michal Simek
parent
b5a88e9d95
commit
c2db55499a
@@ -45,6 +45,5 @@ config ZYNQ_SDHCI_MAX_FREQ
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default 200000000
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source "board/xilinx/Kconfig"
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source "board/xilinx/versal-net/Kconfig"
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endif
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@@ -1,17 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# Copyright (C) 2020 - 2022, Xilinx, Inc.
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# Copyright (C) 2022, Advanced Micro Devices, Inc.
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#
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if ARCH_VERSAL_NET
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config CMD_VERSAL_NET
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bool "Enable Versal NET specific commands"
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default y
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depends on ZYNQMP_FIRMWARE
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help
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Select this to enable Versal NET specific commands.
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Commands like versalnet loadpdi are enabled by this.
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endif
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@@ -7,4 +7,3 @@
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#
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obj-y := board.o
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obj-$(CONFIG_CMD_VERSAL_NET) += cmds.o
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@@ -22,6 +22,7 @@
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include <zynqmp_firmware.h>
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#include <versalpl.h>
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#include "../common/board.h"
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#include <linux/bitfield.h>
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@@ -30,10 +31,21 @@
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_FPGA_VERSALPL)
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static xilinx_desc versalpl = {
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xilinx_versal_net, csu_dma, 1, &versal_op, 0, &versal_op, NULL,
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FPGA_LEGACY
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};
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#endif
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int board_init(void)
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{
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printf("EL Level:\tEL%d\n", current_el());
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#if defined(CONFIG_FPGA_VERSALPL)
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fpga_init();
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fpga_add(fpga_xilinx, &versalpl);
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#endif
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return 0;
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}
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@@ -1,80 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2023, Advanced Micro Devices, Inc.
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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#include <cpu_func.h>
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#include <command.h>
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#include <log.h>
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#include <memalign.h>
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#include <versalpl.h>
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#include <vsprintf.h>
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#include <zynqmp_firmware.h>
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/**
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* do_versalnet_load_pdi - Handle the "versalnet load pdi" command-line command
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* @cmdtp: Command data struct pointer
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* @flag: Command flag
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* @argc: Command-line argument count
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* @argv: Array of command-line arguments
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*
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* Processes the Versal NET load pdi command
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*
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* Return: return 0 on success, Error value if command fails.
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* CMD_RET_USAGE incase of incorrect/missing parameters.
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*/
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static int do_versalnet_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc,
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char * const argv[])
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{
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u32 buf_lo, buf_hi;
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u32 ret_payload[PAYLOAD_ARG_CNT];
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ulong addr, *pdi_buf;
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size_t len;
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int ret;
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if (argc != cmdtp->maxargs) {
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debug("pdi_load: incorrect parameters passed\n");
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return CMD_RET_USAGE;
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}
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addr = simple_strtol(argv[1], NULL, 16);
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if (!addr) {
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debug("pdi_load: zero pdi_data address\n");
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return CMD_RET_USAGE;
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}
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len = hextoul(argv[2], NULL);
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if (!len) {
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debug("pdi_load: zero size\n");
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return CMD_RET_USAGE;
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}
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pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN);
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if ((ulong)addr != (ulong)pdi_buf) {
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memcpy((void *)pdi_buf, (void *)addr, len);
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debug("Pdi addr:0x%lx aligned to 0x%lx\n",
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addr, (ulong)pdi_buf);
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}
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flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len);
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buf_lo = lower_32_bits((ulong)pdi_buf);
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buf_hi = upper_32_bits((ulong)pdi_buf);
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ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
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buf_hi, 0, ret_payload);
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if (ret)
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printf("PDI load failed with err: 0x%08x\n", ret);
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return cmd_process_error(cmdtp, ret);
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}
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U_BOOT_LONGHELP(versalnet,
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"loadpdi addr len - Load pdi image\n"
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"load pdi image at ddr address 'addr' with pdi image size 'len'\n");
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U_BOOT_CMD_WITH_SUBCMDS(versalnet, "Versal NET sub-system", versalnet_help_text,
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U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1,
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do_versalnet_load_pdi));
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@@ -74,6 +74,8 @@ CONFIG_SIMPLE_PM_BUS=y
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CONFIG_CLK_VERSAL=y
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CONFIG_DFU_RAM=y
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CONFIG_ARM_FFA_TRANSPORT=y
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CONFIG_FPGA_XILINX=y
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CONFIG_FPGA_VERSALPL=y
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CONFIG_ZYNQ_GPIO=y
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CONFIG_DM_I2C=y
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CONFIG_SYS_I2C_CADENCE=y
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@@ -34,6 +34,7 @@ typedef enum { /* typedef xilinx_family */
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xilinx_zynq, /* Zynq Family */
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xilinx_zynqmp, /* ZynqMP Family */
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xilinx_versal, /* Versal Family */
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xilinx_versal_net, /* Versal NET Family */
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max_xilinx_type /* insert all new types before this */
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} xilinx_family; /* end, typedef xilinx_family */
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