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xilinx: mbv: Remove redundancy in MB-V defconfigs

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Removes redundant configuration options from MB-V platform defconfigs
targeting both modes. Common settings are now placed in
xilinx_mbv32_defconfig, which is included via the #include <configs/...>.
This approach centralizes configuration management, reduces duplication,
and makes future maintenance easier.

Signed-off-by: Padmarao Begari <padmarao.begari@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/585f96d85b656803bd382ac25425d68998f24ed5.1759393175.git.michal.simek@amd.com
This commit is contained in:
Padmarao Begari
2025-10-02 10:19:38 +02:00
committed by Michal Simek
parent 4c606b165b
commit d413e228ed
3 changed files with 6 additions and 140 deletions
Download Patch File Download Diff File Expand all files Collapse all files

49
configs/xilinx_mbv32_smode_defconfig
View File

@@ -1,50 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0xe00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
CONFIG_SPL_STACK=0x80200000
CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL_SIZE_LIMIT=0x40000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x40600000
CONFIG_DEBUG_UART_CLOCK=1000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0
CONFIG_TARGET_XILINX_MBV=y
#include <configs/xilinx_mbv32_defconfig>
CONFIG_SPL_OPENSBI_LOAD_ADDR=0x80100000
CONFIG_RISCV_SMODE=y
# CONFIG_SPL_SMP is not set
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_BOARD_INIT is not set
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
# CONFIG_CMD_MII is not set
CONFIG_CMD_TIMER=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_MTD=y
CONFIG_DEBUG_UART_UARTLITE=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_XILINX_UARTLITE=y
# CONFIG_RISCV_TIMER is not set
CONFIG_XILINX_TIMER=y
# CONFIG_BINMAN_FDT is not set
CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb"
CONFIG_PANIC_HANG=y
CONFIG_SPL_GZIP=y

47
configs/xilinx_mbv64_defconfig
View File

@@ -1,47 +1,4 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0xe00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
CONFIG_ENV_SIZE=0x20000
#include <configs/xilinx_mbv32_defconfig>
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64"
CONFIG_SPL_STACK=0x80200000
CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL_SIZE_LIMIT=0x40000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x40600000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0
CONFIG_DEBUG_UART=y
CONFIG_TARGET_XILINX_MBV=y
CONFIG_ARCH_RV64I=y
# CONFIG_SPL_SMP is not set
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_BOARD_INIT is not set
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_SYS_MALLOC=y
# CONFIG_CMD_MII is not set
CONFIG_CMD_TIMER=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_MTD=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_XILINX_UARTLITE=y
CONFIG_XILINX_TIMER=y
# CONFIG_BINMAN_FDT is not set
CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb"
CONFIG_PANIC_HANG=y
CONFIG_SPL_GZIP=y

50
configs/xilinx_mbv64_smode_defconfig
View File

@@ -1,51 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0xe00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64"
CONFIG_SPL_STACK=0x80200000
CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SYS_BOOTM_LEN=0x800000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL_SIZE_LIMIT=0x40000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x40600000
CONFIG_DEBUG_UART_CLOCK=1000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0
CONFIG_TARGET_XILINX_MBV=y
#include <configs/xilinx_mbv64_defconfig>
CONFIG_SPL_OPENSBI_LOAD_ADDR=0x80100000
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
# CONFIG_SPL_SMP is not set
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_BOARD_INIT is not set
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_HAVE_INIT_STACK=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
# CONFIG_CMD_MII is not set
CONFIG_CMD_TIMER=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_MTD=y
CONFIG_DEBUG_UART_UARTLITE=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_XILINX_UARTLITE=y
# CONFIG_RISCV_TIMER is not set
CONFIG_XILINX_TIMER=y
# CONFIG_BINMAN_FDT is not set
CONFIG_BINMAN_DTB="./arch/riscv/dts/xilinx-binman.dtb"
CONFIG_PANIC_HANG=y
CONFIG_SPL_GZIP=y