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clk: mediatek: remove CLOCK_PARENT_* aliases

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Remove the CLOCK_* aliases of the CLOCK_PARENT_* macros. One name for
each flag is sufficient.

Signed-off-by: David Lechner <dlechner@baylibre.com>
This commit is contained in:
David Lechner
2025-12-11 16:32:10 -06:00
committed by Tom Rini
parent f646b7749a
commit e21edf2620
5 changed files with 9 additions and 14 deletions
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4
drivers/clk/mediatek/clk-mt7981.c
View File

@@ -521,7 +521,7 @@ static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
.flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,
.flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN,
};
static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
@@ -531,7 +531,7 @@ static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
.fdivs = infra_fixed_divs,
.muxes = infra_muxes,
.gates = infracfg_gates,
.flags = CLK_INFRASYS,
.flags = CLK_PARENT_INFRASYS,
};
static const struct udevice_id mt7981_fixed_pll_compat[] = {

6
drivers/clk/mediatek/clk-mt7986.c
View File

@@ -519,7 +519,7 @@ static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
.fdivs_offs = CLK_APMIXED_NR_CLK,
.xtal_rate = 40 * MHZ,
.fclks = fixed_pll_clks,
.flags = CLK_APMIXED,
.flags = CLK_PARENT_APMIXED,
};
static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
@@ -528,7 +528,7 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
.fclks = top_fixed_clks,
.fdivs = top_fixed_divs,
.muxes = top_muxes,
.flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,
.flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN,
};
static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
@@ -538,7 +538,7 @@ static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
.fdivs = infra_fixed_divs,
.muxes = infra_muxes,
.gates = infracfg_gates,
.flags = CLK_INFRASYS,
.flags = CLK_PARENT_INFRASYS,
};
static const struct udevice_id mt7986_fixed_pll_compat[] = {

4
drivers/clk/mediatek/clk-mt7987.c
View File

@@ -46,7 +46,7 @@ static const struct mtk_fixed_clk apmixedsys_mtk_plls[] = {
static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = {
.fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
.fclks = apmixedsys_mtk_plls,
.flags = CLK_APMIXED,
.flags = CLK_PARENT_APMIXED,
.xtal_rate = 40 * MHZ,
};
@@ -442,7 +442,7 @@ static const struct mtk_clk_tree mt7987_topckgen_clk_tree = {
.muxes_offs = CLK_TOP_NETSYS_SEL,
.fdivs = topckgen_mtk_fixed_factors,
.muxes = topckgen_mtk_muxes,
.flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,
.flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN,
.xtal_rate = MT7987_XTAL_RATE,
};

4
drivers/clk/mediatek/clk-mt7988.c
View File

@@ -773,7 +773,7 @@ static const struct mtk_gate infracfg_mtk_gates[] = {
static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
.fdivs_offs = ARRAY_SIZE(apmixedsys_mtk_plls),
.fclks = apmixedsys_mtk_plls,
.flags = CLK_APMIXED,
.flags = CLK_PARENT_APMIXED,
.xtal_rate = 40 * MHZ,
};
@@ -783,7 +783,7 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
.fclks = topckgen_mtk_fixed_clks,
.fdivs = topckgen_mtk_fixed_factors,
.muxes = topckgen_mtk_muxes,
.flags = CLK_BYPASS_XTAL | CLK_TOPCKGEN,
.flags = CLK_BYPASS_XTAL | CLK_PARENT_TOPCKGEN,
.xtal_rate = 40 * MHZ,
};

5
drivers/clk/mediatek/clk-mtk.h
View File

@@ -41,11 +41,6 @@
#define CLK_PARENT_MIXED BIT(8)
#define CLK_PARENT_MASK GENMASK(8, 4)
/* alias to reference clk type */
#define CLK_APMIXED CLK_PARENT_APMIXED
#define CLK_TOPCKGEN CLK_PARENT_TOPCKGEN
#define CLK_INFRASYS CLK_PARENT_INFRASYS
#define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
/* struct mtk_pll_data - hardware-specific PLLs data */