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configs: qemu-sbsa: Define GIC register base address

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If GICV3 is enabled, GICD_BASE and GICR_BASE are needed at
arch/arm/cpu/armv8/start.S.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
This commit is contained in:
Kunihiko Hayashi
2025-09-10 18:23:26 +09:00
committed by Tom Rini
parent c85b8071e7
commit e246e2b658
1 changed files with 4 additions and 0 deletions
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4
include/configs/qemu-sbsa.h
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@@ -86,4 +86,8 @@
#define CFG_SYS_INIT_RAM_ADDR SBSA_MEM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE 0x1000000
/* Generic Interrupt Controller Definitions */
#define GICD_BASE SBSA_GIC_DIST_BASE_ADDR
#define GICR_BASE SBSA_GIC_REDIST_BASE_ADDR
#endif /* __CONFIG_H */