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pinctrl: mediatek: set array size for reg_cals

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Set the size of the reg_cals arrays to PINCTRL_PIN_REG_MAX to in all
affected mediatek pinctrl drivers. This is needed to avoid potential
out-of-bounds accesses when they is used in mtk_hw_pin_field_get().
All array members need to be initialized since the code loops from 0
to PINCTRL_PIN_REG_MAX - 1. mt7622_reg_cals was already defined this
way, but the others were not.

Signed-off-by: David Lechner <dlechner@baylibre.com>
This commit is contained in:
David Lechner
2026-01-13 17:25:52 -06:00
committed by Tom Rini
parent 712b257406
commit e63e2e797e
10 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/pinctrl/mediatek/pinctrl-mt7623.c
View File

@@ -388,7 +388,7 @@ static const struct mtk_pin_field_calc mt7623_pin_r0_range[] = {
PIN_FIELD16(261, 261, 0x140, 0x10, 10, 1),
};
static const struct mtk_pin_reg_calc mt7623_reg_cals[] = {
static const struct mtk_pin_reg_calc mt7623_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7623_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7623_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7623_pin_di_range),

2
drivers/pinctrl/mediatek/pinctrl-mt7629.c
View File

@@ -80,7 +80,7 @@ static const struct mtk_pin_field_calc mt7629_pin_drv_range[] = {
PIN_FIELD(70, 78, 0x7600, 0x10, 0, 4),
};
static const struct mtk_pin_reg_calc mt7629_reg_cals[] = {
static const struct mtk_pin_reg_calc mt7629_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7629_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7629_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7629_pin_di_range),

2
drivers/pinctrl/mediatek/pinctrl-mt7981.c
View File

@@ -494,7 +494,7 @@ static const struct mtk_pin_field_calc mt7981_pin_r1_range[] = {
PIN_FIELD_BASE(39, 39, 3, 0x40, 0x10, 1, 1),
};
static const struct mtk_pin_reg_calc mt7981_reg_cals[] = {
static const struct mtk_pin_reg_calc mt7981_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7981_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7981_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7981_pin_di_range),

2
drivers/pinctrl/mediatek/pinctrl-mt7986.c
View File

@@ -415,7 +415,7 @@ static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = {
PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1),
};
static const struct mtk_pin_reg_calc mt7986_reg_cals[] = {
static const struct mtk_pin_reg_calc mt7986_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7986_pin_di_range),

2
drivers/pinctrl/mediatek/pinctrl-mt7987.c
View File

@@ -386,7 +386,7 @@ static const struct mtk_pin_field_calc mt7987_pin_r1_range[] = {
PIN_FIELD_BASE(49, 49, IOCFG_TL_BASE, 0x50, 0x10, 8, 1),
};
static const struct mtk_pin_reg_calc mt7987_reg_cals[] = {
static const struct mtk_pin_reg_calc mt7987_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7987_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7987_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7987_pin_di_range),

2
drivers/pinctrl/mediatek/pinctrl-mt7988.c
View File

@@ -606,7 +606,7 @@ static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = {
PIN_FIELD_BASE(83, 83, IOCFG_TR_BASE, 0x90, 0x10, 15, 1),
};
static const struct mtk_pin_reg_calc mt7988_reg_cals[] = {
static const struct mtk_pin_reg_calc mt7988_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range),

2
drivers/pinctrl/mediatek/pinctrl-mt8365.c
View File

@@ -223,7 +223,7 @@ static const struct mtk_pin_field_calc mt8365_pin_drv_range[] = {
PIN_FIELD_DRV(136, 144, 0x770, 24),
};
static const struct mtk_pin_reg_calc mt8365_reg_cals[] = {
static const struct mtk_pin_reg_calc mt8365_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8365_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8365_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8365_pin_di_range),

2
drivers/pinctrl/mediatek/pinctrl-mt8512.c
View File

@@ -178,7 +178,7 @@ static const struct mtk_pin_field_calc mt8512_pin_drv_range[] = {
PIN_FIELDS(112, 115, 0x760, 0x10, 16, 4),
};
static const struct mtk_pin_reg_calc mt8512_reg_cals[] = {
static const struct mtk_pin_reg_calc mt8512_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8512_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8512_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8512_pin_di_range),

2
drivers/pinctrl/mediatek/pinctrl-mt8516.c
View File

@@ -184,7 +184,7 @@ static const struct mtk_pin_field_calc mt8516_pin_drv_range[] = {
PIN_FIELD(117, 120, 0xd70, 0x10, 0, 4),
};
static const struct mtk_pin_reg_calc mt8516_reg_cals[] = {
static const struct mtk_pin_reg_calc mt8516_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8516_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8516_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8516_pin_di_range),

2
drivers/pinctrl/mediatek/pinctrl-mt8518.c
View File

@@ -205,7 +205,7 @@ static const struct mtk_pin_field_calc mt8518_pin_drv_range[] = {
PIN_FIELD(116, 119, 0xd60, 0x10, 4, 4),
};
static const struct mtk_pin_reg_calc mt8518_reg_cals[] = {
static const struct mtk_pin_reg_calc mt8518_reg_cals[PINCTRL_PIN_REG_MAX] = {
[PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8518_pin_mode_range),
[PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8518_pin_dir_range),
[PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8518_pin_di_range),