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riscv: Add Kconfig options to distinguish Zaamo and Zalrsc

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Ratified on Apr. 2024, the original RISC-V "A" extension is now split
into two separate extensions, "Zaamo" for atomic operations and "Zalrsc"
for load-reserved/store-conditional instructions.

For now, we've already seen real-world designs implement the Zalrsc
extension only[2]. As U-Boot mainly runs with only one HART, we could
easily support these designs by not using AMO instructions in the
hard-written assembly if necessary, for which this patch introduces two
new Kconfig options to indicate the availability of "Zaamo" and "Zalrsc".

Note that even with this patch, "A" extension is specified in the ISA
string passed to the compiler as long as one of "Zaamo" or "Zalrsc" is
available, since they're only recognized with a quite recent version of
GCC/Clang. The compiler usually doesn't automatically generate atomic
instructions unless the source explicitly instructs it to do so, thus
this should be safe.

Link: d94c64c63e # [1]
Link: https://lore.kernel.org/u-boot/20250729162035.209849-9-uros.stajic@htecgroup.com/ # [2]
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Yao Zi
2025-09-02 08:19:30 +00:00
committed by Leo Yu-Chi Liang
parent cb1a70a856
commit fde7702c9b
2 changed files with 23 additions and 1 deletions
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17
arch/riscv/Kconfig
View File

@@ -343,10 +343,27 @@ endmenu
config RISCV_ISA_A
bool "Standard extension for Atomic Instructions"
depends on RISCV_ISA_ZAAMO && RISCV_ISA_ZALRSC
default y
help
Adds "A" to the ISA string passed to the compiler.
config RISCV_ISA_ZAAMO
bool "Standard extension for Atomic Memory Operations"
default y
help
Indicates the platform supports Zaamo extension for atomic memory
operations. Hand-written Assembly routines won't use AMO
instructions if set to n.
config RISCV_ISA_ZALRSC
bool "Standard extension for LR/SC instructions"
default y
help
Indicates the platform supports Zalrsc extension for load-reserved
and store-conditional isntructions. Hand-written assembly routines
won't use LR/SC instructions if set to n.
config RISCV_ISA_ZICBOM
bool "Zicbom support"
depends on !SYS_DISABLE_DCACHE_OPS

7
arch/riscv/Makefile
View File

@@ -11,7 +11,12 @@ ifeq ($(CONFIG_ARCH_RV32I),y)
ARCH_BASE = rv32im
ABI_BASE = ilp32
endif
ifeq ($(CONFIG_RISCV_ISA_A),y)
# GCC starts to recognize "Zaamo" and "Zalrsc" from version 15, which is quite
# recent. We don't bother checking the exact compiler version, but pass "A"
# extension for -march as long as one of "Zaamo" or "Zalrsc" is available.
ifeq ($(findstring y,$(CONFIG_RISCV_ISA_A) \
$(CONFIG_RISCV_ISA_ZAAMO) \
$(CONFIG_RISCV_ISA_ZALRSC)),y)
ARCH_A = a
endif
ifeq ($(CONFIG_RISCV_ISA_F),y)