drivers: clock_control: kinetis scg support

add driver and dts-binding for kinetis_scg driver
used on ke1xz

Signed-off-by: Hake Huang <hake.huang@nxp.com>
Signed-off-by: Michael Galda <michael.galda@nxp.com>
This commit is contained in:
Hake Huang
2025-11-07 20:23:43 +08:00
committed by Anas Nashif
parent 31311c4023
commit 00e5a399cc
2 changed files with 7 additions and 3 deletions

View File

@@ -46,8 +46,9 @@ static int mcux_scg_get_rate(const struct device *dev,
case KINETIS_SCG_BUS_CLK:
clock_name = kCLOCK_BusClk;
break;
#if !(defined(CONFIG_SOC_MKE17Z7) || defined(CONFIG_SOC_MKE17Z9) \
|| defined(CONFIG_SOC_SERIES_MCXE24X))
#if !(defined(CONFIG_SOC_MKE17Z7) || defined(CONFIG_SOC_MKE17Z9) || defined(CONFIG_SOC_MKE15Z7)\
|| defined(CONFIG_SOC_MKE15Z4) || defined(CONFIG_SOC_MKE16Z4)\
|| defined(CONFIG_SOC_SERIES_MCXE24X))
case KINETIS_SCG_FLEXBUS_CLK:
clock_name = kCLOCK_FlexBusClk;
break;
@@ -70,7 +71,7 @@ static int mcux_scg_get_rate(const struct device *dev,
break;
#endif /* (defined(FSL_FEATURE_SCG_HAS_SPLL) && FSL_FEATURE_SCG_HAS_SPLL) */
#if (defined(FSL_FEATURE_SCG_HAS_LPFLL) && FSL_FEATURE_SCG_HAS_LPFLL)
case KINETIS_SCG_SPLL_CLK:
case KINETIS_SCG_LPFLL_CLK:
clock_name = kCLOCK_ScgLpFllClk;
break;
#endif /* (defined(FSL_FEATURE_SCG_HAS_LPFLL) && FSL_FEATURE_SCG_HAS_LPFLL) */
@@ -137,6 +138,8 @@ static int mcux_scg_init(const struct device *dev)
CLOCK_SetClkOutSel(kClockClkoutSelFirc);
#elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(spll_clk))
CLOCK_SetClkOutSel(kClockClkoutSelSysPll);
#elif DT_SAME_NODE(DT_CLOCKS_CTLR(MCUX_SCG_CLOCK_NODE(clkout_clk)), MCUX_SCG_CLOCK_NODE(lpfll_clk))
CLOCK_SetClkOutSel(kClockClkoutSelSysLpfll);
#else
#error Unsupported SCG clkout clock source
#endif

View File

@@ -29,5 +29,6 @@
#define KINETIS_SCG_FIRC_ASYNC_DIV2_CLK 13U
#define KINETIS_SCG_SPLL_ASYNC_DIV1_CLK 14U
#define KINETIS_SCG_SPLL_ASYNC_DIV2_CLK 15U
#define KINETIS_SCG_LPFLL_CLK 16U
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_KINETIS_SCG_H_ */