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drivers: sdhc: add SDHC driver for PSE84 & cy8cproto_062_4343w

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- add SDHC driver code to support both SDMMC and SDIO fucntion
- add SDHC dts node and Kconfig
- add clock configuration for SDHC

Signed-off-by: Kevin Chan <kevin.chan3@infineon.com>
This commit is contained in:
Kevin Chan
2025-12-12 14:51:57 -08:00
committed by Henrik Brix Andersen
parent 642127e1d7
commit 0c950801d3
14 changed files with 1406 additions and 360 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.dts
View File

@@ -77,6 +77,12 @@ uart2: &scb2 {
};
};
&clk_hf4 {
clock-div = <1>;
clocks = <&fll0>;
status = "okay";
};
&sdhc0 {
status = "okay";
@@ -85,6 +91,13 @@ uart2: &scb2 {
&p2_1_sdio_data1 &p2_2_sdio_data2 &p2_3_sdio_data3>;
pinctrl-names = "default";
bus-width = <4>;
max-bus-freq = <50000000>;
min-bus-freq = <400000>;
power-delay-ms = <1000>;
no-1-8-v;
clocks = <&clk_hf4>;
/* Wi-Fi configuration */
airoc-wifi {
status = "okay";

30
boards/infineon/kit_pse84_eval/kconfig.defconfig Normal file
View File

@@ -0,0 +1,30 @@
# Copyright (c) 2025 Infineon Technologies AG,
# or an affiliate of Infineon Technologies AG.
#
# SPDX-License-Identifier: Apache-2.0
if BOARD_KIT_PSE84_EVAL_PSE846GPS2DBZC4A_M55
if WIFI
# Select AIROC part and module
choice AIROC_PART
default CYW55500
endchoice
choice CYW55500_MODULE
default CYW55513IUBG_SM
endchoice
# Enable L2 Ethernet
config NET_L2_ETHERNET
default y
# Heap Pool Size
config HEAP_MEM_POOL_ADD_SIZE_BOARD
int
default 15000
endif # WIFI
endif # BOARD_KIT_PSE84_EVAL_PSE846GPS2DBZC4A_M55

72
boards/infineon/kit_pse84_eval/kit_pse84_eval_common-pinctrl.dtsi
View File

@@ -13,3 +13,75 @@
&p6_5_scb2_uart_rx {
input-enable;
};
&p21_0_sdhc0_card_cmd {
drive-push-pull;
input-enable;
drive-strength = "half";
};
&p12_0_sdhc0_clk_card {
drive-push-pull;
input-enable;
drive-strength = "half";
};
&p12_1_sdhc0_card_dat_3to0 {
drive-push-pull;
input-enable;
drive-strength = "half";
};
&p12_2_sdhc0_card_dat_3to0 {
drive-push-pull;
input-enable;
drive-strength = "half";
};
&p12_4_sdhc0_card_dat_3to0 {
drive-push-pull;
input-enable;
drive-strength = "half";
};
&p12_5_sdhc0_card_dat_3to0 {
drive-push-pull;
input-enable;
drive-strength = "half";
};
&p7_0_sdhc1_card_cmd {
drive-push-pull;
input-enable;
drive-strength = "half";
};
&p7_1_sdhc1_clk_card {
drive-push-pull;
input-enable;
drive-strength = "half";
};
&p7_3_sdhc1_card_dat_3to0 {
drive-push-pull;
input-enable;
drive-strength = "half";
};
&p7_5_sdhc1_card_dat_3to0 {
drive-push-pull;
input-enable;
drive-strength = "half";
};
&p7_6_sdhc1_card_dat_3to0 {
drive-push-pull;
input-enable;
drive-strength = "half";
};
&p7_7_sdhc1_card_dat_3to0 {
drive-push-pull;
input-enable;
drive-strength = "half";
};

8
boards/infineon/kit_pse84_eval/kit_pse84_eval_common.dtsi
View File

@@ -78,6 +78,10 @@ uart2: &scb2 {
status = "okay";
};
&gpio_prt11 {
status = "okay";
};
&gpio_prt13 {
status = "okay";
};
@@ -89,3 +93,7 @@ uart2: &scb2 {
&gpio_prt16 {
status = "okay";
};
&gpio_prt17 {
status = "okay";
};

65
boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.dts
View File

@@ -61,3 +61,68 @@
&mcwdt1 {
status = "okay";
};
&peri1_group2_8bit_0 {
status = "okay";
resource-type = <IFX_RSC_SDHC>;
resource-instance = <0>;
clock-div = <2>;
};
&peri1_group3_8bit_0 {
status = "okay";
resource-type = <IFX_RSC_SDHC>;
resource-instance = <1>;
clock-div = <2>;
};
&sdhc0 {
status = "okay";
/* SDIO pins */
pinctrl-0 = <&p21_0_sdhc0_card_cmd &p12_0_sdhc0_clk_card &p12_1_sdhc0_card_dat_3to0
&p12_2_sdhc0_card_dat_3to0 &p12_4_sdhc0_card_dat_3to0
&p12_5_sdhc0_card_dat_3to0>;
pinctrl-names = "default";
clocks = <&peri1_group2_8bit_0>;
bus-width = <4>;
max-bus-freq = <50000000>;
min-bus-freq = <400000>;
power-delay-ms = <1000>;
no-1-8-v;
/* Wi-Fi configuration */
airoc-wifi {
status = "okay";
compatible = "infineon,airoc-wifi";
/* Wi-Fi control gpios */
wifi-reg-on-gpios = <&gpio_prt11 6 GPIO_ACTIVE_HIGH>;
wifi-host-wake-gpios = <&gpio_prt11 4 GPIO_ACTIVE_HIGH>;
};
};
&sdhc1 {
status = "okay";
/* SDHC pins */
pinctrl-0 = <&p7_0_sdhc1_card_cmd &p7_1_sdhc1_clk_card &p7_3_sdhc1_card_dat_3to0
&p7_5_sdhc1_card_dat_3to0 &p7_6_sdhc1_card_dat_3to0
&p7_7_sdhc1_card_dat_3to0>;
pinctrl-names = "default";
clocks = <&peri1_group3_8bit_0>;
bus-width = <4>;
max-bus-freq = <100000000>;
min-bus-freq = <400000>;
power-delay-ms = <1000>;
/* Card detect gpios */
cd-gpios = <&gpio_prt17 7 GPIO_PULL_UP>;
sdmmc {
compatible = "zephyr,sdmmc-disk";
disk-name = "SD";
status = "okay";
};
};

1
boards/infineon/kit_pse84_eval/kit_pse84_eval_m55.yaml
View File

@@ -18,3 +18,4 @@ supported:
- pinctrl
- uart
- spi
- sdhc

27
drivers/clock_control/clock_control_infineon_peri_clock.c
View File

@@ -50,6 +50,11 @@ struct ifx_peri_clock_data {
#define IFX_SCB5_PCLK_CLOCK PCLK_SCB5_CLOCK_SCB_EN
#endif
#if defined(CY_IP_MXSDHC)
#define IFX_SDHC0_PCLK_CLOCK PCLK_SDHC0_CLK_HF
#define IFX_SDHC1_PCLK_CLOCK PCLK_SDHC1_CLK_HF
#endif
#define CLK_FRAC_DIV_MODE 0x02
en_clk_dst_t ifx_cat1_scb_get_clock_index(uint32_t block_num)
@@ -101,6 +106,21 @@ en_clk_dst_t ifx_cat1_tcpwm_get_clock_index(uint32_t block_num, uint32_t channel
return clk;
}
en_clk_dst_t ifx_cat1_sdhc_get_clock_index(uint32_t block_num, uint32_t channel)
{
en_clk_dst_t clk = -EINVAL;
#if defined(CY_IP_MXSDHC)
if (block_num == 0) {
clk = (en_clk_dst_t)((uint32_t)IFX_SDHC0_PCLK_CLOCK);
} else {
clk = (en_clk_dst_t)((uint32_t)IFX_SDHC1_PCLK_CLOCK);
}
#endif
return clk;
}
static int ifx_cat1_peri_clock_init(const struct device *dev)
{
struct ifx_peri_clock_data *const data = dev->data;
@@ -134,6 +154,13 @@ static int ifx_cat1_peri_clock_init(const struct device *dev)
en_clk_dst_t clk_idx = ifx_cat1_tcpwm_get_clock_index(
data->hw_resource.block_num, data->hw_resource.channel_num);
ifx_cat1_utils_peri_pclk_set_divider(clk_idx, &data->clock, data->divider - 1);
ifx_cat1_utils_peri_pclk_assign_divider(clk_idx, &data->clock);
ifx_cat1_utils_peri_pclk_enable_divider(clk_idx, &data->clock);
} else if (data->hw_resource.type == IFX_RSC_SDHC) {
en_clk_dst_t clk_idx = ifx_cat1_sdhc_get_clock_index(data->hw_resource.block_num,
data->hw_resource.channel_num);
ifx_cat1_utils_peri_pclk_set_divider(clk_idx, &data->clock, data->divider - 1);
ifx_cat1_utils_peri_pclk_assign_divider(clk_idx, &data->clock);
ifx_cat1_utils_peri_pclk_enable_divider(clk_idx, &data->clock);

2
drivers/sdhc/CMakeLists.txt
View File

@@ -14,7 +14,7 @@ zephyr_library_sources_ifdef(CONFIG_SAM_HSMCI sam_hsmci.c)
zephyr_library_sources_ifdef(CONFIG_SAM_SDMMC sam_sdmmc.c)
zephyr_library_sources_ifdef(CONFIG_SDHC_AMBIQ sdhc_ambiq.c)
zephyr_library_sources_ifdef(CONFIG_SDHC_ESP32 sdhc_esp32.c)
zephyr_library_sources_ifdef(CONFIG_SDHC_INFINEON_CAT1 infineon_sdio.c)
zephyr_library_sources_ifdef(CONFIG_SDHC_INFINEON_CAT1_PDL sdhc_infineon.c)
zephyr_library_sources_ifdef(CONFIG_SDHC_MAX32 sdhc_max32.c)
zephyr_library_sources_ifdef(CONFIG_SDHC_RENESAS_RA sdhc_renesas_ra.c)
zephyr_library_sources_ifdef(CONFIG_SDHC_STM32_SDIO sdhc_stm32.c)

24
drivers/sdhc/Kconfig.infineon
View File

@@ -1,23 +1,29 @@
# Infineon CAT1 SDHC configuration options
# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# Copyright (c) 2025 Infineon Technologies AG,
# or an affiliate of Infineon Technologies AG.
#
# SPDX-License-Identifier: Apache-2.0
config SDHC_INFINEON_CAT1
bool "Infineon CAT1 SDHC driver"
config SDHC_INFINEON_CAT1_PDL
bool "Infineon SDHC driver"
default y
depends on DT_HAS_INFINEON_SDHC_SDIO_ENABLED
select USE_INFINEON_SDIO
select SDHC_SUPPORTS_NATIVE_MODE
select SDHC_SUPPORTS_UHS
select PINCTRL
help
This option enables the SDHC driver for Infineon CAT1 family.
This option enables the PDL based SDHC driver for Infineon family.
if SDHC_INFINEON_CAT1
if SDHC_INFINEON_CAT1_PDL
config SDHC_INIT_PRIORITY
default 70
endif
config SDHC_BUFFER_ALIGNMENT
default DCACHE_LINE_SIZE if DCACHE
default 1
help
SDHC buffer should aligned to the value of DCACHE_LINE_SIZE when placed in a cacheable region.
endif #SDHC_INFINEON_CAT1_PDL

341
drivers/sdhc/infineon_sdio.c
View File

@@ -1,341 +0,0 @@
/*
* Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
* an affiliate of Cypress Semiconductor Corporation
*
* SPDX-License-Identifier: Apache-2.0
*
*/
/**
* @brief SDIO driver for Infineon CAT1 MCU family.
*
* This driver support only SDIO protocol of the SD interface for general
* I/O functions.
*
* Refer to the SD Specifications Part 1 SDIO Specifications Version 4.10 for more
* information on the SDIO protocol and specifications.
*
* Features
* - Supports 4-bit interface
* - Supports Ultra High Speed (UHS-I) mode
* - Supports Default Speed (DS), High Speed (HS), SDR12, SDR25 and SDR50 speed modes
* - Supports SDIO card interrupts in both 1-bit SD and 4-bit SD modes
* - Supports Standard capacity (SDSC), High capacity (SDHC) and
* Extended capacity (SDXC) memory
*
* Note (limitations):
* - current version of ifx_cat1_sdio supports only following set of commands:
* > GO_IDLE_STATE (CMD0)
* > SEND_RELATIVE_ADDR (CMD3)
* > IO_SEND_OP_COND (CMD5)
* > SELECT_CARD (CMD7)
* > VOLTAGE_SWITCH (CMD11)
* > GO_INACTIVE_STATE (CMD15)
* > IO_RW_DIRECT (CMD52)
* > IO_RW_EXTENDED (CMD53)
*/
#define DT_DRV_COMPAT infineon_sdhc_sdio
#include <zephyr/kernel.h>
#include <zephyr/devicetree.h>
#include <zephyr/drivers/sdhc.h>
#include <zephyr/sd/sd_spec.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/gpio.h>
#include <zephyr/logging/log.h>
#include <soc.h>
#include <zephyr/drivers/pinctrl.h>
#include <cyhal_hw_resources.h>
#include <cyhal_sdhc.h>
#include <cyhal_sdio.h>
#include <cyhal_gpio.h>
LOG_MODULE_REGISTER(ifx_cat1_sdio, CONFIG_SDHC_LOG_LEVEL);
#include <zephyr/irq.h>
#define IFX_CAT1_SDIO_F_MIN (SDMMC_CLOCK_400KHZ)
#define IFX_CAT1_SDIO_F_MAX (SD_CLOCK_50MHZ)
struct ifx_cat1_sdio_config {
const struct pinctrl_dev_config *pincfg;
SDHC_Type *reg_addr;
uint8_t irq_priority;
};
struct ifx_cat1_sdio_data {
cyhal_sdio_t sdio_obj;
cyhal_resource_inst_t hw_resource;
cyhal_sdio_configurator_t cyhal_sdio_config;
enum sdhc_clock_speed clock_speed;
enum sdhc_bus_width bus_width;
void *sdio_cb_user_data;
sdhc_interrupt_cb_t sdio_cb;
};
static uint32_t sdio_rca;
static const cy_stc_sd_host_init_config_t host_config = {false, CY_SD_HOST_DMA_ADMA2, false};
static cy_en_sd_host_card_capacity_t sd_host_card_capacity = CY_SD_HOST_SDSC;
static cy_en_sd_host_card_type_t sd_host_card_type = CY_SD_HOST_NOT_EMMC;
static cy_stc_sd_host_sd_card_config_t sd_host_sd_card_config = {
.lowVoltageSignaling = false,
.busWidth = CY_SD_HOST_BUS_WIDTH_4_BIT,
.cardType = &sd_host_card_type,
.rca = &sdio_rca,
.cardCapacity = &sd_host_card_capacity,
};
/* List of available SDHC instances */
static SDHC_Type *const IFX_CAT1_SDHC_BASE_ADDRESSES[CY_IP_MXSDHC_INSTANCES] = {
#ifdef SDHC0
SDHC0,
#endif /* ifdef SDHC0 */
#ifdef SDHC1
SDHC1,
#endif /* ifdef SDHC1 */
};
static int32_t _get_hw_block_num(SDHC_Type *reg_addr)
{
uint32_t i;
for (i = 0u; i < CY_IP_MXSDHC_INSTANCES; i++) {
if (IFX_CAT1_SDHC_BASE_ADDRESSES[i] == reg_addr) {
return i;
}
}
return -EINVAL;
}
static int ifx_cat1_sdio_reset(const struct device *dev)
{
struct ifx_cat1_sdio_data *dev_data = dev->data;
cyhal_sdhc_software_reset((cyhal_sdhc_t *)&dev_data->sdio_obj);
return 0;
}
static int ifx_cat1_sdio_set_io(const struct device *dev, struct sdhc_io *ios)
{
cy_rslt_t ret;
struct ifx_cat1_sdio_data *dev_data = dev->data;
cyhal_sdio_cfg_t config = {.frequencyhal_hz = ios->clock};
/* NOTE: Set bus width, set card power, set host signal voltage,
* set I/O timing does not support in current version of driver
*/
/* Set host clock */
if ((dev_data->clock_speed != ios->clock) && (ios->clock != 0)) {
if ((ios->clock > IFX_CAT1_SDIO_F_MAX) || (ios->clock < IFX_CAT1_SDIO_F_MIN)) {
return -EINVAL;
}
ret = cyhal_sdio_configure(&dev_data->sdio_obj, &config);
if (ret != CY_RSLT_SUCCESS) {
return -ENOTSUP;
}
dev_data->clock_speed = ios->clock;
}
return 0;
}
static int ifx_cat1_sdio_card_busy(const struct device *dev)
{
struct ifx_cat1_sdio_data *dev_data = dev->data;
return cyhal_sdio_is_busy(&dev_data->sdio_obj) ? 1 : 0;
}
static int ifx_cat1_sdio_request(const struct device *dev, struct sdhc_command *cmd,
struct sdhc_data *data)
{
struct ifx_cat1_sdio_data *dev_data = dev->data;
int ret;
switch (cmd->opcode) {
case CYHAL_SDIO_CMD_GO_IDLE_STATE:
case CYHAL_SDIO_CMD_SEND_RELATIVE_ADDR:
case CYHAL_SDIO_CMD_IO_SEND_OP_COND:
case CYHAL_SDIO_CMD_SELECT_CARD:
case CYHAL_SDIO_CMD_VOLTAGE_SWITCH:
case CYHAL_SDIO_CMD_GO_INACTIVE_STATE:
case CYHAL_SDIO_CMD_IO_RW_DIRECT:
ret = cyhal_sdio_send_cmd(&dev_data->sdio_obj, CYHAL_SDIO_XFER_TYPE_READ,
cmd->opcode, cmd->arg, cmd->response);
if (ret != CY_RSLT_SUCCESS) {
LOG_ERR("cyhal_sdio_send_cmd failed ret = %d \r\n", ret);
}
break;
case CYHAL_SDIO_CMD_IO_RW_EXTENDED:
cyhal_sdio_transfer_type_t direction;
direction = (cmd->arg & BIT(SDIO_CMD_ARG_RW_SHIFT)) ? CYHAL_SDIO_XFER_TYPE_WRITE
: CYHAL_SDIO_XFER_TYPE_READ;
ret = cyhal_sdio_bulk_transfer(&dev_data->sdio_obj, direction, cmd->arg, data->data,
data->blocks * data->block_size, cmd->response);
if (ret != CY_RSLT_SUCCESS) {
LOG_ERR("cyhal_sdio_bulk_transfer failed ret = %d \r\n", ret);
}
break;
default:
ret = -ENOTSUP;
}
return ret;
}
static int ifx_cat1_sdio_get_card_present(const struct device *dev)
{
return 1;
}
static int ifx_cat1_sdio_get_host_props(const struct device *dev, struct sdhc_host_props *props)
{
memset(props, 0, sizeof(*props));
props->f_max = IFX_CAT1_SDIO_F_MAX;
props->f_min = IFX_CAT1_SDIO_F_MIN;
props->host_caps.bus_4_bit_support = true;
props->host_caps.high_spd_support = true;
props->host_caps.sdr50_support = true;
props->host_caps.sdio_async_interrupt_support = true;
props->host_caps.vol_330_support = true;
return 0;
}
static int ifx_cat1_sdio_enable_interrupt(const struct device *dev, sdhc_interrupt_cb_t callback,
int sources, void *user_data)
{
struct ifx_cat1_sdio_data *data = dev->data;
const struct ifx_cat1_sdio_config *cfg = dev->config;
if (sources != SDHC_INT_SDIO) {
return -ENOTSUP;
}
if (callback == NULL) {
return -EINVAL;
}
/* Record SDIO callback parameters */
data->sdio_cb = callback;
data->sdio_cb_user_data = user_data;
/* Enable CARD INTERRUPT event */
cyhal_sdio_enable_event(&data->sdio_obj, CYHAL_SDIO_CARD_INTERRUPT,
cfg->irq_priority, true);
return 0;
}
static int ifx_cat1_sdio_disable_interrupt(const struct device *dev, int sources)
{
struct ifx_cat1_sdio_data *data = dev->data;
const struct ifx_cat1_sdio_config *cfg = dev->config;
if (sources != SDHC_INT_SDIO) {
return -ENOTSUP;
}
data->sdio_cb = NULL;
data->sdio_cb_user_data = NULL;
/* Disable CARD INTERRUPT event */
cyhal_sdio_enable_event(&data->sdio_obj, CYHAL_SDIO_CARD_INTERRUPT,
cfg->irq_priority, false);
return 0;
}
static void ifx_cat1_sdio_event_callback(void *callback_arg, cyhal_sdio_event_t event)
{
const struct device *dev = callback_arg;
struct ifx_cat1_sdio_data *data = dev->data;
if ((event == CYHAL_SDIO_CARD_INTERRUPT) && (data->sdio_cb != NULL)) {
data->sdio_cb(dev, SDHC_INT_SDIO, data->sdio_cb_user_data);
}
}
static int ifx_cat1_sdio_init(const struct device *dev)
{
cy_rslt_t ret;
struct ifx_cat1_sdio_data *data = dev->data;
const struct ifx_cat1_sdio_config *config = dev->config;
/* Configure dt provided device signals when available */
ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
if (ret) {
return ret;
}
/* Dedicate SDIO HW resource */
data->hw_resource.type = CYHAL_RSC_SDHC;
data->hw_resource.block_num = _get_hw_block_num(config->reg_addr);
data->hw_resource.channel_num = 0;
/* Initialize the SDIO peripheral */
data->cyhal_sdio_config.resource = &data->hw_resource;
data->cyhal_sdio_config.host_config = &host_config,
data->cyhal_sdio_config.card_config = &sd_host_sd_card_config,
data->cyhal_sdio_config.gpios.cmd = NC;
data->cyhal_sdio_config.gpios.clk = NC;
data->cyhal_sdio_config.gpios.data[0] = NC;
data->cyhal_sdio_config.gpios.data[1] = NC;
data->cyhal_sdio_config.gpios.data[2] = NC;
data->cyhal_sdio_config.gpios.data[3] = NC;
data->cyhal_sdio_config.clock = NULL;
ret = cyhal_sdio_init_cfg(&data->sdio_obj, &data->cyhal_sdio_config);
if (ret != CY_RSLT_SUCCESS) {
LOG_ERR("cyhal_sdio_init_cfg failed ret = %d \r\n", ret);
return ret;
}
/* Register callback for SDIO events */
cyhal_sdio_register_callback(&data->sdio_obj, ifx_cat1_sdio_event_callback, (void *)dev);
return 0;
}
static DEVICE_API(sdhc, ifx_cat1_sdio_api) = {
.reset = ifx_cat1_sdio_reset,
.request = ifx_cat1_sdio_request,
.set_io = ifx_cat1_sdio_set_io,
.get_card_present = ifx_cat1_sdio_get_card_present,
.card_busy = ifx_cat1_sdio_card_busy,
.get_host_props = ifx_cat1_sdio_get_host_props,
.enable_interrupt = ifx_cat1_sdio_enable_interrupt,
.disable_interrupt = ifx_cat1_sdio_disable_interrupt,
};
#define IFX_CAT1_SDHC_INIT(n) \
\
PINCTRL_DT_INST_DEFINE(n); \
\
static const struct ifx_cat1_sdio_config ifx_cat1_sdio_##n##_config = { \
.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
.reg_addr = (SDHC_Type *)DT_INST_REG_ADDR(n), \
.irq_priority = DT_INST_IRQ(n, priority)}; \
\
static struct ifx_cat1_sdio_data ifx_cat1_sdio_##n##_data; \
\
DEVICE_DT_INST_DEFINE(n, &ifx_cat1_sdio_init, NULL, &ifx_cat1_sdio_##n##_data, \
&ifx_cat1_sdio_##n##_config, POST_KERNEL, CONFIG_SDHC_INIT_PRIORITY, \
&ifx_cat1_sdio_api);
DT_INST_FOREACH_STATUS_OKAY(IFX_CAT1_SDHC_INIT)

1141
drivers/sdhc/sdhc_infineon.c Normal file
View File

File diff suppressed because it is too large Load Diff

10
drivers/wifi/infineon/Kconfig.airoc
View File

@@ -244,6 +244,11 @@ config CYW955513SDM2WLIPA_SM
bool "CYW955513SDM2WLIPA_SM"
help
Infineon CYW955513SDM2WLIPA (SM) module
config CYW55513IUBG_SM
bool "CYW55513IUBG_SM"
help
Infineon CYW55513IUBG (SM) module
endchoice
choice CYW55572_MODULE
@@ -254,11 +259,6 @@ config CYW955573M2IPA1_SM
bool "CYW955573M2IPA1_SM"
help
Infineon CYW955573M2IPA1 (SM) module
config CYW55513IUBG_SM
bool "CYW55513IUBG_SM"
help
Infineon CYW55513IUBG (SM) module
endchoice
endif # AIROC_WIFI

25
dts/bindings/sdhc/infineon,sdhc-sdio.yaml
View File

@@ -1,5 +1,5 @@
# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
# an affiliate of Cypress Semiconductor Corporation
# Copyright (c) 2025 Infineon Technologies AG,
# or an affiliate of Infineon Technologies AG.
#
# SPDX-License-Identifier: Apache-2.0
@@ -24,3 +24,24 @@ properties:
system-interrupts:
description: Required for cat1c devices
bus-width:
type: int
default: 4
description: |
bus width for SDMMC access, defaults to the minimum necessary
number of bus lines
enum:
- 1
- 4
- 8
no-1-8-v:
type: boolean
description: |
The SD/MMC bus on the board doesn't support the 1.8V voltage,
Which disables UHS-I, HS200 and HS400 support.
cd-gpios:
type: phandle-array
description: Card Detect pin

7
modules/hal_infineon/CMakeLists.txt
View File

@@ -85,8 +85,11 @@ endif()
if(CONFIG_WIFI_AIROC)
add_subdirectory(whd-expansion)
## Add core-lib sources for CAT1 devices
add_subdirectory_ifndef(CONFIG_SOC_FAMILY_INFINEON_CAT1 core-lib)
if(NOT CONFIG_SOC_FAMILY_INFINEON_CAT1
AND NOT CONFIG_SOC_FAMILY_PSOC6_LEGACY
AND NOT CONFIG_SOC_FAMILY_INFINEON_EDGE)
add_subdirectory(core-lib)
endif()
## Add abstraction-rtos sources
add_subdirectory_ifndef(CONFIG_SOC_FAMILY_INFINEON_CAT1 abstraction-rtos)