board: add '32f967_dv' development board (minimal build support)

Minimal board definition for the Elan em32f967 SOC:
- Includes DTS, YAML, and Kconfig files
- Provides board.cmake with misc-flasher for CI/build
- Actual flashing is not included in this PR

Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>

boards/elan/32f967_dv/32f967_dv.dts

@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2024 ELAN Microelectronics Corp.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm/armv7-m.dtsi>
+#include <elan/em32fxxx.dtsi>
+#include <elan/em32f967-pinctrl.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "ELAN EM32F967 Development Board";
+	compatible = "elan,em32f967_dv";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash-controller = &em32_flash_controller;
+		zephyr,flash = &flash0;
+	};
+};
+
+&clk_ahb {
+	status = "okay";
+};
+
+&clk_apb {
+	clocks = <&clk_ahb>;
+	status = "okay";
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(272)>;
+};
+
+&spi2 {
+	status = "disabled";
+	pinctrl-0 = <&spi2_sck_pb5 &spi2_miso_pb6 &spi2_mosi_pb7>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpiob 4 GPIO_ACTIVE_LOW>;
+};
+
+&uart1 {
+	status = "disabled";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_rx_pa1 &uart1_tx_pa2>;
+	pinctrl-names = "default";
+};
+
+&em32_flash_controller {
+	status = "okay";
+};
+
+&gpioa {
+	status = "disabled";
+};
+
+&gpiob {
+	status = "disabled";
+};
+
+zephyr_udc0: &usbd {
+	status = "disabled";
+};
+
+&uid {
+	status = "disabled";
+};
+
+&bbram0 {
+	status = "disabled";
+};
+
+&trng0 {
+	status = "disabled";
+};
+
+&wdt0 {
+	status = "disabled";
+};
+
+&crypto0 {
+	status = "disabled";
+};
+
+/* Enable Timer controllers */
+&timer1 {
+	status = "disabled";
+};
+
+&timer2 {
+	status = "disabled";
+};
+
+/* Enable RTC */
+&rtc0 {
+	status = "disabled";
+};
+
+/* Enable PWM Controller - PWMB N output on PA3 */
+&pwm0 {
+	status = "disabled";
+	use-port-a;			/* Use Port A pins (PWM_S=0) */
+	output-type = <1>;		/* N output only */
+	pinctrl-0 = <&pwmb_pa3_n>;
+	pinctrl-names = "default";
+};
+
+&sysctrl {
+	status = "disabled";
+};
+
+&pwrctrl {
+	status = "disabled";
+};
+
+&clkctrl {
+	status = "disabled";
+};

boards/elan/32f967_dv/32f967_dv.yaml

@@ -0,0 +1,12 @@
+identifier: 32f967_dv
+name: ELAN EM32F967 dv Board
+vendor: elan
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+testing:
+  default: false
+supported: []
+ram: 272
+flash: 536

boards/elan/32f967_dv/Kconfig.32f967_dv

@@ -0,0 +1,6 @@
+# Copyright (c) 2025 ELAN Microelectronics Corp.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_32F967_DV
+	select SOC_EM32F967

boards/elan/32f967_dv/Kconfig.defconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2025 ELAN Microelectronics Corp.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config UART_USE_RUNTIME_CONFIGURE
+	default n
+
+config UART_INTERRUPT_DRIVEN
+	default n
+
+config UART_ASYNC_API
+	default n

boards/elan/32f967_dv/board.cmake

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_set_flasher_ifnset(misc-flasher)
+board_finalize_runner_args(misc-flasher)

boards/elan/32f967_dv/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: 32f967_dv
+  full_name: ELAN EM32F967
+  vendor: elan
+  socs:
+    - name: em32f967

boards/elan/32f967_dv/doc/index.rst

@@ -0,0 +1,84 @@
+.. zephyr:board:: 32f967_dv
+
+Elan 32f967_dv
+##############
+
+Overview
+********
+
+The Elan 32f967_dv is a B2B development board based on the Elan em32f967
+SoC (ARM Cortex-M4). This board is used to validate the initial SoC
+integration with Zephyr.
+
+Hardware
+********
+
+The platform provides the following hardware components:
+
+- SoC: Elan em32f967 (ARM Cortex-M4)
+- Maximum CPU frequency: 96 MHz
+- Embedded Flash: 536 KB
+- Embedded RAM: 272 KB
+- UART (debug via soldered jump wires, no dedicated connector)
+- SPI
+- GPIO
+- PWM
+- USB (used for firmware flashing and application communication)
+- Watchdog Timer (WDT)
+- Backup domain registers (accessed via Zephyr BBRAM interface)
+- True Random Number Generator (TRNG)
+- Hardware Crypto Engine
+- Timer
+- Real-Time Clock (RTC)
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+- **UART_1 TX/RX** : PA2 / PA1
+- **SPI_2 NSS/SCK/MISO/MOSI** : PB4 / PB5 / PB6 / PB7
+- **PWM_0 LED** : PA3
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+This board does not use a standard flashing interface such as J-Link or OpenOCD.
+
+Flashing
+========
+
+The flashing tool is distributed only to Elan's customers for production and
+evaluation purposes. It is not publicly available.
+
+At this stage, the Zephyr ``west flash`` command is not supported.
+
+You can build applications in the usual way. Here is an example for
+the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: 32f967_dv
+   :goals: build
+
+Debugging
+=========
+
+You can debug an application in the usual way. Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: 32f967_dv
+   :goals: debug
+
+References
+**********
+
+Documentation for this board and the Elan em32f967 SoC is available to Elan customers.
+Please contact Elan for datasheets, technical reference manuals, and tooling information.

boards/elan/index.rst

@@ -0,0 +1,10 @@
+.. _boards-elan:
+
+Elan Microelectronics Corp.
+###########################
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*

dts/arm/elan/em32f967-pinctrl.dtsi

@@ -0,0 +1,343 @@
+/*
+ * Copyright (c) 2024 ELAN Microelectronics Corp.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/em32f967-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@40030200 {
+			compatible = "elan,em32-pinctrl";
+			reg = <0x40030200 0x100>;
+			reg-names = "iomux";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#pinctrl-cells = <1>;
+
+			/*
+			 * EM32F967 Pin Control Configurations
+			 * Based on EM32F967_Complete_Specification_v1.0.md
+			 *
+			 * Pin Functions per specification:
+			 * - PA0-PA6: 5V tolerant pins
+			 * - PA11-PA15: 3V pins (SWCLK/SWDIO, GPIO, Debug)
+			 * - PB0-PB15: 3V pins
+			 */
+
+			/* UART1 Pin Configurations - PA1/PA2 */
+			/*  MUX 010 = AF2, IP_Share[6] =1*/
+			/omit-if-no-ref/ uart1_rx_pa1: uart1_rx_pa1 {
+				pinmux = <EM32F967_PINMUX('A', 1, AF2)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart1_tx_pa2: uart1_tx_pa2 {
+				pinmux = <EM32F967_PINMUX('A', 2, AF2)>;
+				bias-pull-up;
+			};
+
+			/* UART2 Pin Configurations - PA4/PA5 */
+			/*  MUX 010 = AF2, IP_Share[7] =1*/
+			uart2_rx_pa4: uart2_rx_pa4 {
+				pinmux = <EM32F967_PINMUX('A', 4, AF2)>;
+				bias-pull-up;
+			};
+
+			uart2_tx_pa5: uart2_tx_pa5 {
+				pinmux = <EM32F967_PINMUX('A', 5, AF2)>;
+				bias-pull-up;
+			};
+
+			/* UART3 Pin Configurations - PB0/PB1 */
+			/* Default Disable, IOMUX 110 = AF6,  */
+			uart3_rx_pb0: uart3_rx_pb0 {
+				pinmux = <EM32F967_PINMUX('B', 0, AF6)>;
+				bias-pull-up;
+			};
+
+			uart3_tx_pb1: uart3_tx_pb1 {
+				pinmux = <EM32F967_PINMUX('B', 1, AF6)>;
+				bias-pull-up;
+			};
+
+			/* SPI1 (Elan SPI) Pin Configurations - PB0/PB1/PB2/PB3 (Default) */
+			/* SPI1 functions on PB0-PB3: MUX 001 = AF1, IP_Share[1:0]=00 */
+			spi1_cs_pb0: spi1_cs_pb0 {
+				pinmux = <EM32F967_PINMUX('B', 0, AF1)>;
+				drive-strength = <4>;
+			};
+
+			spi1_sck_pb1: spi1_sck_pb1 {
+				pinmux = <EM32F967_PINMUX('B', 1, AF1)>;
+				drive-strength = <4>;
+			};
+
+			spi1_miso_pb2: spi1_miso_pb2 {
+				pinmux = <EM32F967_PINMUX('B', 2, AF1)>;
+				bias-pull-up;
+			};
+
+			spi1_mosi_pb3: spi1_mosi_pb3 {
+				pinmux = <EM32F967_PINMUX('B', 3, AF1)>;
+				drive-strength = <4>;
+			};
+
+			/* SPI2 Pin Configurations - PB4/PB5/PB6/PB7 (Default) */
+			/* ARM SSP2 master functions on PB4-PB7: MUX 010 = AF2, IP_Share[3:2]=00 */
+			spi2_cs_pb4: spi2_cs_pb4 {
+				pinmux = <EM32F967_PINMUX('B', 4, AF2)>;  /* SSP_SS2 - MUX 010 */
+				drive-strength = <4>;
+			};
+
+			spi2_sck_pb5: spi2_sck_pb5 {
+				pinmux = <EM32F967_PINMUX('B', 5, AF2)>;  /* SSP_SCK2 - MUX 010 */
+				drive-strength = <4>;
+			};
+
+			spi2_miso_pb6: spi2_miso_pb6 {
+				pinmux = <EM32F967_PINMUX('B', 6, AF2)>;  /* SSP_SPIRX2 - MUX 010 */
+			};
+
+			spi2_mosi_pb7: spi2_mosi_pb7 {
+				pinmux = <EM32F967_PINMUX('B', 7, AF2)>;  /* SSP_SPITX2 - MUX 010 */
+				drive-strength = <4>;
+			};
+
+			/* I2C1 Pin Configurations - PB0/PB1 */
+			/* IOMUX 101 = AF5, IP_Share[8]=1 */
+			i2c1_scl_pb0: i2c1_scl_pb0 {
+				pinmux = <EM32F967_PINMUX('B', 0, AF5)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			i2c1_sda_pb1: i2c1_sda_pb1 {
+				pinmux = <EM32F967_PINMUX('B', 1, AF5)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/* I2C2 Pin Configurations - PA4/PA5 */
+			/* IOMUX 100 = AF4, IP_Share[9]=0 */
+			i2c2_scl_pb6: i2c2_scl_pb6 {
+				pinmux = <EM32F967_PINMUX('A', 4, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			i2c2_sda_pb7: i2c2_sda_pb7 {
+				pinmux = <EM32F967_PINMUX('A', 5, AF4)>;
+				bias-pull-up;
+				drive-open-drain;
+			};
+
+			/*
+			 * PWM Pin Configurations
+			 * EM32F967 supports 6 PWM channels (PWMA-PWMF)
+			 * with two pin assignment options:
+			 *
+			 * Primary Assignment (PWM_S=0, IP_Share[18]=0, IOMUX=AF7):
+			 *   PWMA: PA0 (P), PA1 (N)
+			 *   PWMB: PA2 (P), PA3 (N)
+			 *   PWMC: PA4 (P), PA5 (N)
+			 *   PWMD/PWME/PWMF share with PWMA/PWMB/PWMC respectively
+			 *
+			 * Alternative Assignment (PWM_S=1, IP_Share[18]=1, IOMUX=AF1):
+			 *   PWMA: PB10 (P), PB11 (N)
+			 *   PWMB: PB12 (P), PB13 (N)
+			 *   PWMC: PB14 (P), PB15 (N)
+			 *   PWMD/PWME/PWMF share with PWMA/PWMB/PWMC respectively
+			 */
+
+			/* Primary PWM Pin Configurations - PA0-PA5 (PWM_S=0) */
+			/* IOMUX 111 = AF7 for PWM on Port A */
+			/omit-if-no-ref/ pwma_pa0_p: pwma_pa0_p {
+				pinmux = <EM32F967_PINMUX('A', 0, AF7)>;  /* PWMA Positive */
+				drive-strength = <4>;
+			};
+
+			/omit-if-no-ref/ pwma_pa1_n: pwma_pa1_n {
+				pinmux = <EM32F967_PINMUX('A', 1, AF7)>;  /* PWMA/PWMD Negative */
+				drive-strength = <4>;
+			};
+
+			/omit-if-no-ref/ pwmb_pa2_p: pwmb_pa2_p {
+				pinmux = <EM32F967_PINMUX('A', 2, AF7)>;  /* PWMB Positive */
+				drive-strength = <4>;
+			};
+
+			/omit-if-no-ref/ pwmb_pa3_n: pwmb_pa3_n {
+				pinmux = <EM32F967_PINMUX('A', 3, AF7)>;  /* PWMB/PWME Negative */
+				drive-strength = <4>;
+			};
+
+			/omit-if-no-ref/ pwmc_pa4_p: pwmc_pa4_p {
+				pinmux = <EM32F967_PINMUX('A', 4, AF7)>;  /* PWMC Positive */
+				drive-strength = <4>;
+			};
+
+			/omit-if-no-ref/ pwmc_pa5_n: pwmc_pa5_n {
+				pinmux = <EM32F967_PINMUX('A', 5, AF7)>;  /* PWMC/PWMF Negative */
+				drive-strength = <4>;
+			};
+
+			/* Alternative PWM Pin Configurations - PB10-PB15 (PWM_S=1) */
+			/* IOMUX 001 = AF1 for PWM on Port B */
+			/omit-if-no-ref/ pwma_pb10_p: pwma_pb10_p {
+				pinmux = <EM32F967_PINMUX('B', 10, AF1)>;  /* PWMA Positive */
+				drive-strength = <4>;
+			};
+
+			/omit-if-no-ref/ pwma_pb11_n: pwma_pb11_n {
+				pinmux = <EM32F967_PINMUX('B', 11, AF1)>;  /* PWMA/PWMD Negative */
+				drive-strength = <4>;
+			};
+
+			/omit-if-no-ref/ pwmb_pb12_p: pwmb_pb12_p {
+				pinmux = <EM32F967_PINMUX('B', 12, AF1)>;  /* PWMB Positive */
+				drive-strength = <4>;
+			};
+
+			/omit-if-no-ref/ pwmb_pb13_n: pwmb_pb13_n {
+				pinmux = <EM32F967_PINMUX('B', 13, AF1)>;  /* PWMB/PWME Negative */
+				drive-strength = <4>;
+			};
+
+			/omit-if-no-ref/ pwmc_pb14_p: pwmc_pb14_p {
+				pinmux = <EM32F967_PINMUX('B', 14, AF1)>;  /* PWMC Positive */
+				drive-strength = <4>;
+			};
+
+			/omit-if-no-ref/ pwmc_pb15_n: pwmc_pb15_n {
+				pinmux = <EM32F967_PINMUX('B', 15, AF1)>;  /* PWMC/PWMF Negative */
+				drive-strength = <4>;
+			};
+
+			/* GPIO Pin Configurations - Default GPIO mode */
+			gpio_pa0: gpio_pa0 {
+				pinmux = <EM32F967_PINMUX('A', 0, GPIO)>;
+			};
+
+			gpio_pa1: gpio_pa1 {
+				pinmux = <EM32F967_PINMUX('A', 1, GPIO)>;
+			};
+
+			gpio_pa2: gpio_pa2 {
+				pinmux = <EM32F967_PINMUX('A', 2, GPIO)>;
+			};
+
+			gpio_pa3: gpio_pa3 {
+				pinmux = <EM32F967_PINMUX('A', 3, GPIO)>;
+			};
+
+			gpio_pa4: gpio_pa4 {
+				pinmux = <EM32F967_PINMUX('A', 4, GPIO)>;
+			};
+
+			gpio_pa5: gpio_pa5 {
+				pinmux = <EM32F967_PINMUX('A', 5, GPIO)>;
+			};
+
+			gpio_pa6: gpio_pa6 {
+				pinmux = <EM32F967_PINMUX('A', 6, GPIO)>;
+			};
+
+			gpio_pa11: gpio_pa11 {
+				pinmux = <EM32F967_PINMUX('A', 11, GPIO)>;
+			};
+
+			gpio_pa12: gpio_pa12 {
+				pinmux = <EM32F967_PINMUX('A', 12, GPIO)>;
+			};
+
+			gpio_pa13: gpio_pa13 {
+				pinmux = <EM32F967_PINMUX('A', 13, GPIO)>;
+			};
+
+			gpio_pa14: gpio_pa14 {
+				pinmux = <EM32F967_PINMUX('A', 14, GPIO)>;
+			};
+
+			gpio_pa15: gpio_pa15 {
+				pinmux = <EM32F967_PINMUX('A', 15, GPIO)>;
+			};
+
+			gpio_pb0: gpio_pb0 {
+				pinmux = <EM32F967_PINMUX('B', 0, GPIO)>;
+			};
+
+			gpio_pb1: gpio_pb1 {
+				pinmux = <EM32F967_PINMUX('B', 1, GPIO)>;
+			};
+
+			gpio_pb2: gpio_pb2 {
+				pinmux = <EM32F967_PINMUX('B', 2, GPIO)>;
+			};
+
+			gpio_pb3: gpio_pb3 {
+				pinmux = <EM32F967_PINMUX('B', 3, GPIO)>;
+			};
+
+			gpio_pb4: gpio_pb4 {
+				pinmux = <EM32F967_PINMUX('B', 4, GPIO)>;
+			};
+
+			gpio_pb5: gpio_pb5 {
+				pinmux = <EM32F967_PINMUX('B', 5, GPIO)>;
+			};
+
+			gpio_pb6: gpio_pb6 {
+				pinmux = <EM32F967_PINMUX('B', 6, GPIO)>;
+			};
+
+			gpio_pb7: gpio_pb7 {
+				pinmux = <EM32F967_PINMUX('B', 7, GPIO)>;
+			};
+
+			gpio_pb8: gpio_pb8 {
+				pinmux = <EM32F967_PINMUX('B', 8, GPIO)>;
+			};
+
+			gpio_pb9: gpio_pb9 {
+				pinmux = <EM32F967_PINMUX('B', 9, GPIO)>;
+			};
+
+			/* UART1 Alternate Pin Configurations - PB8/PB9 */
+			/*  MUX 010 = AF2, IP_Share[6] = 0 (alternate route) */
+			/omit-if-no-ref/ uart1_rx_pb8: uart1_rx_pb8 {
+				pinmux = <EM32F967_PINMUX('B', 8, AF2)>;
+				bias-pull-up;
+			};
+
+			/omit-if-no-ref/ uart1_tx_pb9: uart1_tx_pb9 {
+				pinmux = <EM32F967_PINMUX('B', 9, AF2)>;
+				bias-pull-up;
+			};
+
+			gpio_pb10: gpio_pb10 {
+				pinmux = <EM32F967_PINMUX('B', 10, GPIO)>;
+			};
+
+			gpio_pb11: gpio_pb11 {
+				pinmux = <EM32F967_PINMUX('B', 11, GPIO)>;
+			};
+
+			gpio_pb12: gpio_pb12 {
+				pinmux = <EM32F967_PINMUX('B', 12, GPIO)>;
+			};
+
+			gpio_pb13: gpio_pb13 {
+				pinmux = <EM32F967_PINMUX('B', 13, GPIO)>;
+			};
+
+			gpio_pb14: gpio_pb14 {
+				pinmux = <EM32F967_PINMUX('B', 14, GPIO)>;
+			};
+
+			gpio_pb15: gpio_pb15 {
+				pinmux = <EM32F967_PINMUX('B', 15, GPIO)>;
+			};
+		};
+	};
+};