soc: allwinner: add sun8i h3 soc support

Add initial support for the Allwinner H3 SoC, commonly
found in development boards like the Orange Pi series.

This commit introduces the intial SoC support files:
 - Basic Kconfig configuration and SoC definition
 - MMU region setup for memory management
 - SoC-specific headers and device tree source include

Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>

dts/arm/allwinner/sun8i-h3.dtsi

@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2025 Muhammad Waleed Badar
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <freq.h>
+
+#include <arm/armv7-a.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <1>;
+		};
+
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <2>;
+		};
+
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <3>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		status = "okay";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		gic: interrupt-controller@1c81000 {
+			compatible = "arm,gic-400", "arm,gic-v2", "arm,gic";
+			status = "okay";
+			reg = <0x01c81000 0x1000>,
+			      <0x01c82000 0x2000>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			#address-cells = <0>;
+		};
+
+		uart0: uart@1c28000 {
+			compatible = "ns16550", "snps,dw-apb-uart";
+			reg = <0x01c28000 0x400>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL
+				      IRQ_DEFAULT_PRIORITY>;
+			clock-frequency = <DT_FREQ_M(24)>;
+			status = "disabled";
+		};
+
+		uart1: uart@1c28400 {
+			compatible = "ns16550", "snps,dw-apb-uart";
+			reg = <0x01c28400 0x400>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL
+				      IRQ_DEFAULT_PRIORITY>;
+			clock-frequency = <DT_FREQ_M(24)>;
+			status = "disabled";
+		};
+
+		uart2: uart@1c28800 {
+			compatible = "ns16550", "snps,dw-apb-uart";
+			reg = <0x01c28800 0x400>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL
+				      IRQ_DEFAULT_PRIORITY>;
+			clock-frequency = <DT_FREQ_M(24)>;
+			status = "disabled";
+		};
+
+		uart3: uart@1c28c00 {
+			compatible = "ns16550", "snps,dw-apb-uart";
+			reg = <0x01c28c00 0x400>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL
+				      IRQ_DEFAULT_PRIORITY>;
+			clock-frequency = <DT_FREQ_M(24)>;
+			status = "disabled";
+		};
+	};
+};

soc/allwinner/sun8i_h3/CMakeLists.txt

@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Muhammad Waleed Badar
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources_ifdef(CONFIG_ARM_AARCH32_MMU soc.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")

soc/allwinner/sun8i_h3/Kconfig

@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Muhammad Waleed Badar
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SUN8I_H3
+	select ARM
+	select CPU_CORTEX_A7
+	select ARM_ARCH_TIMER
+	select SYS_CLOCK_EXISTS

soc/allwinner/sun8i_h3/Kconfig.defconfig

@@ -0,0 +1,25 @@
+# Copyright (c) 2025 Muhammad Waleed Badar
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SUN8I_H3
+
+config NUM_IRQS
+	default 156
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+if SERIAL
+
+config UART_NS16550
+	default y
+
+config UART_NS16550_DW8250_DW_APB
+	default y
+
+config UART_NS16550_ACCESS_WORD_ONLY
+	default y
+
+endif # SERIAL
+
+endif

soc/allwinner/sun8i_h3/Kconfig.soc

@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Muhammad Waleed Badar
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SUN8I_H3
+	bool
+
+config SOC
+	default "sun8i_h3" if SOC_SUN8I_H3

soc/allwinner/sun8i_h3/soc.c

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 Muhammad Waleed Badar
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/arch/arm/mmu/arm_mmu.h>
+
+static const struct arm_mmu_region mmu_regions[] = {
+	MMU_REGION_FLAT_ENTRY("vectors", 0, 0x1000, MT_STRONGLY_ORDERED | MPERM_R | MPERM_X),
+
+	MMU_REGION_FLAT_ENTRY("gic", 0x01c81000, 0x3000, MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
+
+	MMU_REGION_FLAT_ENTRY("uart", 0x01c28000, 0x1000, MT_DEVICE | MPERM_R | MPERM_W),
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};

soc/allwinner/sun8i_h3/soc.h

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 Muhammad Waleed Badar
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#ifndef _ASMLANGUAGE
+
+/*
+ * The following definitions are required for the inclusion of the CMSIS
+ * Common Peripheral Access Layer for aarch32 Cortex-A CPUs:
+ */
+
+#define __CORTEX_A 7U
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _SOC__H_ */

soc/allwinner/sun8i_h3/soc.yml

@@ -0,0 +1,4 @@
+series:
+- name: sun8i
+  socs:
+  - name: sun8i_h3