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Bluetooth: controller: Fix disabling of Coded PHY feature

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Fix conditional compilation in nRF5 radio interface so that
when Coded PHY feature is not selected then it does not use
the PPIs required for supporting the feature.

This will allow pwm_nrf5_sw driver to use PPI channels 14 to
19 and support 3 PWM channels. Without the Coded PHY feature
disabled, only PPI 14, 15, 18 and 19 are available for PWM.

Signed-off-by: Vinayak Kariappa Chettimada <vich@nordicsemi.no>
This commit is contained in:
Vinayak Kariappa Chettimada
2018-02-08 11:37:41 +01:00
committed by Carles Cufí
parent b22ab26b10
commit 18f366ca07
2 changed files with 56 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
subsys/bluetooth/controller/hal/nrf5/radio/radio.c
View File

@@ -176,6 +176,7 @@ void radio_pkt_configure(u8_t bits_len, u8_t max_len, u8_t flags)
RADIO_PCNF0_PLEN_Msk;
break;
#if defined(CONFIG_BT_CTLR_PHY_CODED)
#if defined(CONFIG_SOC_NRF52840)
case BIT(2):
extra |= (RADIO_PCNF0_PLEN_LongRange << RADIO_PCNF0_PLEN_Pos) &
@@ -185,6 +186,7 @@ void radio_pkt_configure(u8_t bits_len, u8_t max_len, u8_t flags)
RADIO_PCNF0_TERMLEN_Msk;
break;
#endif /* CONFIG_SOC_NRF52840 */
#endif /* CONFIG_BT_CTLR_PHY_CODED */
}
/* To use same Data Channel PDU structure with nRF5 specific overhead
@@ -395,6 +397,7 @@ static void sw_switch(u8_t dir, u8_t phy_curr, u8_t flags_curr, u8_t phy_next,
hal_radio_txen_on_sw_switch(ppi);
#if defined(CONFIG_BT_CTLR_PHY_CODED)
#if defined(CONFIG_SOC_NRF52840)
if (phy_curr & BIT(2)) {
/* Switching to TX after RX on LE Coded PHY. */
@@ -479,6 +482,7 @@ static void sw_switch(u8_t dir, u8_t phy_curr, u8_t flags_curr, u8_t phy_next,
sw_tifs_toggle);
}
#endif /* CONFIG_SOC_NRF52840 */
#endif /* CONFIG_BT_CTLR_PHY_CODED */
} else {
/* RX */
delay = HAL_RADIO_NS2US_CEIL(
@@ -488,6 +492,7 @@ static void sw_switch(u8_t dir, u8_t phy_curr, u8_t flags_curr, u8_t phy_next,
hal_radio_rxen_on_sw_switch(ppi);
#if defined(CONFIG_BT_CTLR_PHY_CODED)
#if defined(CONFIG_SOC_NRF52840)
if (1) {
u8_t ppi_dis =
@@ -508,6 +513,7 @@ static void sw_switch(u8_t dir, u8_t phy_curr, u8_t flags_curr, u8_t phy_next,
~(HAL_SW_SWITCH_RADIO_ENABLE_S2_PPI_INCLUDE);
}
#endif /* CONFIG_SOC_NRF52840 */
#endif /* CONFIG_BT_CTLR_PHY_CODED */
}
if (delay <
@@ -669,12 +675,14 @@ void radio_tmr_status_reset(void)
HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI_DISABLE |
HAL_RADIO_DISABLE_ON_HCTO_PPI_DISABLE |
HAL_RADIO_END_TIME_CAPTURE_PPI_DISABLE |
#if defined(CONFIG_BT_CTLR_PHY_CODED)
#if defined(CONFIG_SOC_NRF52840)
HAL_TRIGGER_RATEOVERRIDE_PPI_DISABLE |
#if !defined(CONFIG_BT_CTLR_TIFS_HW)
HAL_SW_SWITCH_TIMER_S8_DISABLE_PPI_DISABLE |
#endif /* !CONFIG_BT_CTLR_TIFS_HW */
#endif /* CONFIG_SOC_NRF52840 */
#endif /* CONFIG_BT_CTLR_PHY_CODED */
HAL_TRIGGER_CRYPT_PPI_DISABLE;
#if defined(CONFIG_BOARD_NRFXX_NWTSIM)
@@ -749,7 +757,10 @@ u32_t radio_tmr_start(u8_t trx, u32_t ticks_start, u32_t remainder)
HAL_SW_SWITCH_TIMER_CLEAR_PPI_REGISTER_TASK =
HAL_SW_SWITCH_TIMER_CLEAR_PPI_TASK;
#if !defined(CONFIG_SOC_NRF52840)
#if !defined(CONFIG_BT_CTLR_PHY_CODED) || !defined(CONFIG_SOC_NRF52840)
/* NOTE: PPI channel group disable is setup explicitly in sw_switch
* function when Coded PHY on nRF52840 is supported.
*/
HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_EVT(
HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(0)) =
HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_EVT(
@@ -765,7 +776,8 @@ u32_t radio_tmr_start(u8_t trx, u32_t ticks_start, u32_t remainder)
HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_REGISTER_TASK(
HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI(1)) =
HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_TASK(1);
#endif /* !defined(CONFIG_SOC_NRF52840) */
#endif /* !CONFIG_BT_CTLR_PHY_CODED || !CONFIG_SOC_NRF52840 */
NRF_PPI->CHG[SW_SWITCH_TIMER_TASK_GROUP(0)] =
HAL_SW_SWITCH_GROUP_TASK_DISABLE_PPI_0_INCLUDE |
HAL_SW_SWITCH_RADIO_ENABLE_PPI_0_INCLUDE;
@@ -1080,6 +1092,7 @@ void *radio_ccm_rx_pkt_set(struct ccm *ccm, u8_t phy, void *pkt)
NRF_CCM->ENABLE = CCM_ENABLE_ENABLE_Enabled;
mode = (CCM_MODE_MODE_Decryption << CCM_MODE_MODE_Pos) &
CCM_MODE_MODE_Msk;
#if defined(CONFIG_SOC_SERIES_NRF52X)
/* Enable CCM support for 8-bit length field PDUs. */
mode |= (CCM_MODE_LENGTH_Extended << CCM_MODE_LENGTH_Pos) &
@@ -1100,6 +1113,7 @@ void *radio_ccm_rx_pkt_set(struct ccm *ccm, u8_t phy, void *pkt)
CCM_MODE_DATARATE_Msk;
break;
#if defined(CONFIG_BT_CTLR_PHY_CODED)
#if defined(CONFIG_SOC_NRF52840)
case BIT(2):
mode |= (CCM_MODE_DATARATE_125Kbps <<
@@ -1118,11 +1132,13 @@ void *radio_ccm_rx_pkt_set(struct ccm *ccm, u8_t phy, void *pkt)
NRF_PPI->CHENSET = HAL_TRIGGER_RATEOVERRIDE_PPI_ENABLE;
#if defined(CONFIG_BOARD_NRFXX_NWTSIM)
NRF_PPI_regw_sideeffects();
#endif
#endif /* CONFIG_BOARD_NRFXX_NWTSIM */
break;
#endif /* CONFIG_SOC_NRF52840 */
#endif /* CONFIG_BT_CTLR_PHY_CODED */
}
#endif
#endif /* CONFIG_SOC_SERIES_NRF52X */
NRF_CCM->MODE = mode;
NRF_CCM->CNFPTR = (u32_t)ccm;
NRF_CCM->INPTR = (u32_t)_pkt_scratch;

37
subsys/bluetooth/controller/hal/nrf5/radio/radio_nrf52840.h
View File

@@ -404,28 +404,39 @@ static inline u32_t hal_radio_phy_mode_get(u8_t phy, u8_t flags)
case BIT(0):
default:
mode = RADIO_MODE_MODE_Ble_1Mbit;
#if defined(CONFIG_BT_CTLR_PHY_CODED)
/* Workaround: nRF52840 Engineering A Errata ID 164 */
*(volatile u32_t *)0x4000173c &= ~0x80000000;
#endif /* CONFIG_BT_CTLR_PHY_CODED */
break;
case BIT(1):
mode = RADIO_MODE_MODE_Ble_2Mbit;
#if defined(CONFIG_BT_CTLR_PHY_CODED)
/* Workaround: nRF52840 Engineering A Errata ID 164 */
*(volatile u32_t *)0x4000173c &= ~0x80000000;
mode = RADIO_MODE_MODE_Ble_2Mbit;
#endif /* CONFIG_BT_CTLR_PHY_CODED */
break;
#if defined(CONFIG_BT_CTLR_PHY_CODED)
case BIT(2):
if (flags & 0x01) {
mode = RADIO_MODE_MODE_Ble_LR125Kbit;
} else {
mode = RADIO_MODE_MODE_Ble_LR500Kbit;
}
/* Workaround: nRF52840 Engineering A Errata ID 164 */
*(volatile u32_t *)0x4000173c |= 0x80000000;
*(volatile u32_t *)0x4000173c =
((*(volatile u32_t *)0x4000173c) & 0xFFFFFF00) |
0x5C;
break;
#endif /* CONFIG_BT_CTLR_PHY_CODED */
}
return mode;
@@ -439,12 +450,15 @@ static inline u32_t hal_radio_tx_ready_delay_us_get(u8_t phy, u8_t flags)
return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_US;
case BIT(1):
return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_US;
#if defined(CONFIG_BT_CTLR_PHY_CODED)
case BIT(2):
if (flags & 0x01) {
return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_US;
} else {
return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_US;
}
#endif /* CONFIG_BT_CTLR_PHY_CODED */
}
}
@@ -456,12 +470,15 @@ static inline u32_t hal_radio_rx_ready_delay_us_get(u8_t phy, u8_t flags)
return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_US;
case BIT(1):
return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_US;
#if defined(CONFIG_BT_CTLR_PHY_CODED)
case BIT(2):
if (flags & 0x01) {
return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_US;
} else {
return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_US;
}
#endif /* CONFIG_BT_CTLR_PHY_CODED */
}
}
@@ -473,12 +490,15 @@ static inline u32_t hal_radio_tx_chain_delay_us_get(u8_t phy, u8_t flags)
return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_1M_US;
case BIT(1):
return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_2M_US;
#if defined(CONFIG_BT_CTLR_PHY_CODED)
case BIT(2):
if (flags & 0x01) {
return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_S8_US;
} else {
return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_S2_US;
}
#endif /* CONFIG_BT_CTLR_PHY_CODED */
}
}
@@ -490,12 +510,15 @@ static inline u32_t hal_radio_rx_chain_delay_us_get(u8_t phy, u8_t flags)
return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_1M_US;
case BIT(1):
return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_2M_US;
#if defined(CONFIG_BT_CTLR_PHY_CODED)
case BIT(2):
if (flags & 0x01) {
return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_S8_US;
} else {
return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_S2_US;
}
#endif /* CONFIG_BT_CTLR_PHY_CODED */
}
}
@@ -507,12 +530,15 @@ static inline u32_t hal_radio_tx_ready_delay_ns_get(u8_t phy, u8_t flags)
return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_1M_NS;
case BIT(1):
return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_2M_NS;
#if defined(CONFIG_BT_CTLR_PHY_CODED)
case BIT(2):
if (flags & 0x01) {
return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S8_NS;
} else {
return HAL_RADIO_NRF52840_TXEN_TXIDLE_TX_S2_NS;
}
#endif /* CONFIG_BT_CTLR_PHY_CODED */
}
}
@@ -524,12 +550,15 @@ static inline u32_t hal_radio_rx_ready_delay_ns_get(u8_t phy, u8_t flags)
return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_1M_NS;
case BIT(1):
return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_2M_NS;
#if defined(CONFIG_BT_CTLR_PHY_CODED)
case BIT(2):
if (flags & 0x01) {
return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S8_NS;
} else {
return HAL_RADIO_NRF52840_RXEN_RXIDLE_RX_S2_NS;
}
#endif /* CONFIG_BT_CTLR_PHY_CODED */
}
}
@@ -541,12 +570,15 @@ static inline u32_t hal_radio_tx_chain_delay_ns_get(u8_t phy, u8_t flags)
return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_1M_NS;
case BIT(1):
return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_2M_NS;
#if defined(CONFIG_BT_CTLR_PHY_CODED)
case BIT(2):
if (flags & 0x01) {
return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_S8_NS;
} else {
return HAL_RADIO_NRF52840_TX_CHAIN_DELAY_S2_NS;
}
#endif /* CONFIG_BT_CTLR_PHY_CODED */
}
}
@@ -558,11 +590,14 @@ static inline u32_t hal_radio_rx_chain_delay_ns_get(u8_t phy, u8_t flags)
return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_1M_NS;
case BIT(1):
return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_2M_NS;
#if defined(CONFIG_BT_CTLR_PHY_CODED)
case BIT(2):
if (flags & 0x01) {
return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_S8_NS;
} else {
return HAL_RADIO_NRF52840_RX_CHAIN_DELAY_S2_NS;
}
#endif /* CONFIG_BT_CTLR_PHY_CODED */
}
}