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soc: rename CONFIG_INTEL_CAVS_V25 to CONFIG_SOC_CAVSV25

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Just following the guideline.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit is contained in:
Daniel Leung
2026-01-16 11:14:40 -08:00
committed by Anas Nashif
parent 987722df9d
commit 1dae40fa2e
6 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
boards/intel/adsp/Kconfig.intel_adsp
View File

@@ -2,8 +2,8 @@
# SPDX-License-Identifier: Apache-2.0
config BOARD_INTEL_ADSP
select SOC_INTEL_CAVS_V25 if BOARD_INTEL_ADSP_CAVS25
select SOC_INTEL_CAVS_V25 if BOARD_INTEL_ADSP_CAVS25_TGPH
select SOC_CAVSV25 if BOARD_INTEL_ADSP_CAVS25
select SOC_CAVSV25 if BOARD_INTEL_ADSP_CAVS25_TGPH
select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM
select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM_SIM
select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL

2
drivers/interrupt_controller/intc_cavs.c
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@@ -16,7 +16,7 @@
#include "intc_cavs.h"
#if defined(CONFIG_SMP) && (CONFIG_MP_MAX_NUM_CPUS > 1)
#if defined(CONFIG_SOC_INTEL_CAVS_V25)
#if defined(CONFIG_SOC_CAVSV25)
#define PER_CPU_OFFSET(x) (0x40 * x)
#else
#error "Must define PER_CPU_OFFSET(x) for SoC"

2
soc/intel/intel_adsp/cavs/Kconfig
View File

@@ -15,6 +15,6 @@ config SOC_SERIES_INTEL_ADSP_CAVS
select INTEL_ADSP_MEMORY_IS_MIRRORED
select CACHE_HAS_MIRRORED_MEMORY_REGIONS
config SOC_INTEL_CAVS_V25
config SOC_CAVSV25
select XTENSA_WAITI_BUG
select SCHED_IPI_SUPPORTED

4
soc/intel/intel_adsp/cavs/Kconfig.defconfig.cavs_v25
View File

@@ -1,7 +1,7 @@
# Copyright (c) 2020,2022-2024 Intel Corporation
# SPDX-License-Identifier: Apache-2.0
if SOC_INTEL_CAVS_V25
if SOC_CAVSV25
# For backward compatibility, to be removed
config SOC_SERIES_INTEL_CAVS_V25
@@ -53,4 +53,4 @@ endif
config ADSP_NEED_POWER_ON_CACHE
default y
endif # SOC_INTEL_CAVS_V25
endif # SOC_CAVSV25

6
soc/intel/intel_adsp/cavs/Kconfig.soc
View File

@@ -11,14 +11,14 @@ config SOC_SERIES_INTEL_ADSP_CAVS
config SOC_SERIES
default "intel_adsp_cavs" if SOC_SERIES_INTEL_ADSP_CAVS
config SOC_INTEL_CAVS_V25
config SOC_CAVSV25
bool
select SOC_SERIES_INTEL_ADSP_CAVS
help
Intel Tiger Lake
config SOC
default "cavs25" if SOC_INTEL_CAVS_V25
default "cavs25" if SOC_CAVSV25
config SOC_TOOLCHAIN_NAME
default "intel_tgl_adsp" if SOC_INTEL_CAVS_V25
default "intel_tgl_adsp" if SOC_CAVSV25

2
soc/intel/intel_adsp/common/gdbstub_backend_sram.c
View File

@@ -19,7 +19,7 @@
#include <zephyr/cache.h>
#define RING_SIZE 512
#if CONFIG_SOC_INTEL_CAVS_V25
#if CONFIG_SOC_CAVSV25
#define SOF_GDB_WINDOW_OFFSET 1024
#elif CONFIG_SOC_INTEL_ACE15_MTPM || CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30 || \
CONFIG_SOC_INTEL_ACE40