style: soc: apply coding style on CMakeLists.txt files

Apply the CMake style guidelines to CMakeList.txt files in soc/. Signed-off-by: Josuah Demangeon <me@josuah.net>
2025-11-15 16:41:51 +00:00
parent e6e7fc549e
commit 23662f1e5d
12 changed files with 56 additions and 65 deletions
--- a/soc/intel/intel_adsp/CMakeLists.txt
+++ b/soc/intel/intel_adsp/CMakeLists.txt
@@ -7,11 +7,11 @@ zephyr_include_directories(common)

 add_subdirectory(common)
 if(CONFIG_SOC_SERIES_INTEL_ADSP_ACE)
-	zephyr_include_directories(ace)
-	add_subdirectory(ace)
+  zephyr_include_directories(ace)
+  add_subdirectory(ace)
 endif()
 if(CONFIG_INTEL_ADSP_CAVS)
-	zephyr_include_directories(cavs)
-	add_subdirectory(cavs)
+  zephyr_include_directories(cavs)
+  add_subdirectory(cavs)
 endif()
 zephyr_include_directories(common/include)
--- a/soc/mediatek/mt8xxx/CMakeLists.txt
+++ b/soc/mediatek/mt8xxx/CMakeLists.txt
@@ -9,10 +9,11 @@ zephyr_library_sources_ifdef(CONFIG_SOC_MT8188 ${CONFIG_SOC}/cpuclk.c)
 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/${CONFIG_SOC}/linker.ld CACHE INTERNAL "")

 add_custom_target(dsp_img ALL
-	DEPENDS ${ZEPHYR_FINAL_EXECUTABLE}
-	COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_img.py
-		${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME}
-		${CMAKE_BINARY_DIR}/zephyr/zephyr.img)
+  DEPENDS ${ZEPHYR_FINAL_EXECUTABLE}
+  COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_img.py
+    ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME}
+    ${CMAKE_BINARY_DIR}/zephyr/zephyr.img
+)

 # Sign zephyr.ri using west (if the underlying rimage tool is
 # available; generally it isn't except in SOF builds).  Note that the
@@ -37,9 +38,9 @@ board_set_rimage_target(${CONFIG_SOC})
 set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default rimage key")
 add_custom_target(zephyr.ri ALL DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri)
 add_custom_command(
-	OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
-	COMMENT "Sign with rimage..."
-	COMMAND west $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose> sign
-                     --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR}
-	DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
+  OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
+  COMMENT "Sign with rimage..."
+  COMMAND west $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose> sign
+    --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR}
+  DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
 )
--- a/soc/native/inf_clock/CMakeLists.txt
+++ b/soc/native/inf_clock/CMakeLists.txt
@@ -6,15 +6,15 @@ zephyr_library()
 zephyr_library_compile_definitions(NO_POSIX_CHEATS)

 zephyr_library_sources(
-	soc.c
-	native_tasks.c
-	native_remap.c
-	)
+  soc.c
+  native_tasks.c
+  native_remap.c
+)

 zephyr_library_include_directories(
  ${ZEPHYR_BASE}/kernel/include
  ${ZEPHYR_BASE}/arch/posix/include
-  )
+)

 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/posix/linker.ld CACHE INTERNAL "")

--- a/soc/raspberrypi/rpi_pico/common/CMakeLists.txt
+++ b/soc/raspberrypi/rpi_pico/common/CMakeLists.txt
@@ -4,7 +4,7 @@
 zephyr_include_directories(.)

 zephyr_sources(
-	soc.c
+  soc.c
 )

 zephyr_sources_ifdef(CONFIG_RPI_PICO_ROM_BOOTLOADER rom_bootloader.c)
--- a/soc/snps/hsdk/CMakeLists.txt
+++ b/soc/snps/hsdk/CMakeLists.txt
@@ -12,8 +12,8 @@ if(COMPILER STREQUAL gcc)
 else()
  # MWDT compiler options
  zephyr_compile_options(-arcv2hs -core2 -Xatomic -Xll64 -Xunaligned -Xcode_density
-		   -Xdiv_rem=radix4 -Xswap -Xbitscan -Xmpy_option=qmpyh
-		   -Xshift_assist -Xbarrel_shifter -Xtimer0 -Xtimer1 -Xrtc)
+    -Xdiv_rem=radix4 -Xswap -Xbitscan -Xmpy_option=qmpyh
+    -Xshift_assist -Xbarrel_shifter -Xtimer0 -Xtimer1 -Xrtc)
  zephyr_compile_options_ifdef(CONFIG_FPU -Xfpu_mac -Xfpud_div)

  zephyr_ld_options(-Hlib=hs38_full)
--- a/soc/snps/nsim/arc_classic/em/CMakeLists.txt
+++ b/soc/snps/nsim/arc_classic/em/CMakeLists.txt
@@ -11,22 +11,20 @@ if(COMPILER STREQUAL gcc)
 else()
  # MWDT compiler options
  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_EM -arcv2em -core3 -Xdiv_rem=radix2
-			       -Xmpy_option=mpyd -Xbitscan -Xswap -Xbarrel_shifter
-			       -Xshift_assist -Xdsp2 -Xdsp_complex
-			       -Xdsp_divsqrt=radix2 -Xdsp_itu -Xdsp_accshift=full
-			       -Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
-			       -Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
+    -Xmpy_option=mpyd -Xbitscan -Xswap -Xbarrel_shifter -Xshift_assist -Xdsp2 -Xdsp_complex
+    -Xdsp_divsqrt=radix2 -Xdsp_itu -Xdsp_accshift=full -Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
+    -Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)

  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_EM11D -arcv2em -core3 -Xdiv_rem=radix2
-			       -Xbitscan -Xswap -Xbarrel_shifter
-			       -Xshift_assist -Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
-			       -Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
+    -Xbitscan -Xswap -Xbarrel_shifter
+    -Xshift_assist -Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
+    -Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)

  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_EM11D -Hlib=em9d_nrg_fpusp -Hdsplib)

  if(CONFIG_SOC_NSIM_EM11D)
    set_property(GLOBAL PROPERTY z_arc_dsp_options -Xxy -Xagu_large -Hfxapi -Xdsp2
-              -Xdsp_accshift=full -Xdsp_divsqrt=radix2 -Xdsp_complex -Xdsp_itu
-              -Xdsp_ctrl=postshift,noguard,convergent -Xmpy_option=mpyd)
+      -Xdsp_accshift=full -Xdsp_divsqrt=radix2 -Xdsp_complex -Xdsp_itu
+      -Xdsp_ctrl=postshift,noguard,convergent -Xmpy_option=mpyd)
  endif()
 endif()
--- a/soc/snps/nsim/arc_classic/hs/CMakeLists.txt
+++ b/soc/snps/nsim/arc_classic/hs/CMakeLists.txt
@@ -14,48 +14,42 @@ else()
  # MWDT compiler options

  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS -arcv2hs -core2 -Xatomic
-			       -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
-			       -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
-			       -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
-			       -Xtimer0 -Xtimer1)
+    -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density -Xswap -Xbitscan -Xmpy_option=qmpyh
+    -Xshift_assist -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc -Xtimer0 -Xtimer1)

  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS -Hlib=hs38_full)

  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS_SMP -arcv2hs -core2 -Xatomic
-			       -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
-			       -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
-			       -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
-			       -Xtimer0 -Xtimer1)
+    -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density -Xswap -Xbitscan -Xmpy_option=qmpyh
+    -Xshift_assist -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc -Xtimer0 -Xtimer1)

  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS_SMP -Hlib=hs38_full)

  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS_MPUV6 -arcv2hs -core2 -Xatomic
-			       -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
-			       -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
-			       -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
-			       -Xtimer0 -Xtimer1)
+    -Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density -Xswap -Xbitscan -Xmpy_option=qmpyh
+    -Xshift_assist -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc -Xtimer0 -Xtimer1)

  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS_MPUV6 -Hlib=hs38_full)

  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS5X -arcv3hs -core0 -Xdual_issue -uarch_rev=0:0
-			       -HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh
-			       -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
+    -HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh
+    -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)

  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS5X -Hlib=hs58_full)

  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS5X_SMP -arcv3hs -core0 -Xdual_issue -uarch_rev=0:0
-             -HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh
-             -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
+    -HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh -Xtimer0
+    -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)

  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS5X_SMP -Hlib=hs58_full)

  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS6X -arc64 -core0 -uarch_rev=0:0 -HL -Xatomic=2
-             -Xunaligned -Xmpy_cycles=3 -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
+    -Xunaligned -Xmpy_cycles=3 -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)

  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS6X -Hlib=hs68_full_zephyr)

  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS6X_SMP -arc64 -core0 -uarch_rev=0:0 -HL -Xatomic=2
-             -Xunaligned -Xmpy_cycles=3 -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
+    -Xunaligned -Xmpy_cycles=3 -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)

  zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS6X_SMP -Hlib=hs68_full_zephyr)
 endif()
--- a/soc/snps/nsim/arc_classic/sem/CMakeLists.txt
+++ b/soc/snps/nsim/arc_classic/sem/CMakeLists.txt
@@ -12,10 +12,8 @@ else()
  # MWDT compiler options

  zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_SEM -arcv2em -core3 -Xcode_density
-			       -Xdiv_rem=radix2 -Xswap -Xbitscan -Xmpy_option=mpyd
-			       -Xshift_assist -Xbarrel_shifter -Xdsp2
-			       -Xdsp_complex -Xdsp_divsqrt=radix2
-			       -Xdsp_accshift=limited -Xtimer0 -Xtimer1
-			       -Xsec_timer0 -Xstack_check -Xsec_modes -Xdmac)
+    -Xdiv_rem=radix2 -Xswap -Xbitscan -Xmpy_option=mpyd -Xshift_assist -Xbarrel_shifter -Xdsp2
+    -Xdsp_complex -Xdsp_divsqrt=radix2 -Xdsp_accshift=limited -Xtimer0 -Xtimer1 -Xsec_timer0
+    -Xstack_check -Xsec_modes -Xdmac)

 endif()
--- a/soc/st/stm32/CMakeLists.txt
+++ b/soc/st/stm32/CMakeLists.txt
@@ -2,10 +2,10 @@
 # SPDX-License-Identifier: Apache-2.0

 if(CONFIG_BUILD_WITH_TFM)
-	set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-		#Execute post build script postbuild.sh
-		COMMAND $<TARGET_PROPERTY:tfm,TFM_BINARY_DIR>/api_ns/postbuild.sh ${CROSS_COMPILE}${CC}
-	)
+  set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+    # Execute post build script postbuild.sh
+    COMMAND $<TARGET_PROPERTY:tfm,TFM_BINARY_DIR>/api_ns/postbuild.sh ${CROSS_COMPILE}${CC}
+  )
 endif()

 add_subdirectory(common)
--- a/soc/st/stm32/common/CMakeLists.txt
+++ b/soc/st/stm32/common/CMakeLists.txt
@@ -3,8 +3,8 @@
 zephyr_include_directories(.)

 zephyr_sources(
-	stm32cube_hal.c
-	soc_config.c
+  stm32cube_hal.c
+  soc_config.c
 )

 if(DEFINED CONFIG_STM32_CCM)
--- a/soc/telink/tlsr/tlsr951x/CMakeLists.txt
+++ b/soc/telink/tlsr/tlsr951x/CMakeLists.txt
@@ -2,9 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0

 zephyr_sources(
-	start.S
-	soc_irq.S
-	soc.c
+  start.S
+  soc_irq.S
+  soc.c
 )

 zephyr_include_directories(.)
--- a/soc/ti/mspm0/CMakeLists.txt
+++ b/soc/ti/mspm0/CMakeLists.txt
@@ -5,6 +5,6 @@ set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/li
 add_subdirectory(common)

 if(CONFIG_SOC_FAMILY_TI_MSPM0)
-	string(TOUPPER ${CONFIG_SOC} SDK_SOC_SELECT)
-	zephyr_compile_definitions(-D__${SDK_SOC_SELECT}__)
+  string(TOUPPER ${CONFIG_SOC} SDK_SOC_SELECT)
+  zephyr_compile_definitions(-D__${SDK_SOC_SELECT}__)
 endif()