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arch: riscv: use RISCV_ISA_EXT_F to set CPU_HAS_FPU

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use CONFIG_RISCV_ISA_EXT_F to set CONFIG_CPU_HAS_FPU.
Same for CONFIG_RISCV_ISA_EXT_D and
CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This commit is contained in:
Fin Maaß
2025-10-21 11:15:08 +02:00
committed by Chris Friedt
parent 3be1b9ca7a
commit 24669df207
12 changed files with 11 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/riscv/Kconfig.isa
View File

@@ -45,6 +45,7 @@ config RISCV_ISA_EXT_A
config RISCV_ISA_EXT_F
bool
select CPU_HAS_FPU
help
(F) - Standard Extension for Single-Precision Floating-Point
@@ -56,6 +57,7 @@ config RISCV_ISA_EXT_F
config RISCV_ISA_EXT_D
bool
depends on RISCV_ISA_EXT_F
select CPU_HAS_FPU_DOUBLE_PRECISION
help
(D) - Standard Extension for Double-Precision Floating-Point

5
soc/andestech/ae350/Kconfig
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@@ -61,11 +61,12 @@ config NO_FPU
config SINGLE_PRECISION_FPU
bool "Single precision FPU"
select CPU_HAS_FPU
select RISCV_ISA_EXT_F
config DOUBLE_PRECISION_FPU
bool "Double precision FPU"
select CPU_HAS_FPU_DOUBLE_PRECISION
select RISCV_ISA_EXT_F
select RISCV_ISA_EXT_D
endchoice

1
soc/bflb/bl60x/Kconfig
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@@ -8,7 +8,6 @@ config SOC_SERIES_BL60X
select CACHE_MANAGEMENT
select CLOCK_CONTROL
select CODE_DATA_RELOCATION
select CPU_HAS_FPU
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select FLOAT_HARD

1
soc/bflb/bl61x/Kconfig
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@@ -5,7 +5,6 @@
config SOC_SERIES_BL61X
select CLOCK_CONTROL
select CODE_DATA_RELOCATION
select CPU_HAS_FPU
select DCACHE
select FLOAT_HARD
select FPU

1
soc/bflb/bl70x/Kconfig
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@@ -7,7 +7,6 @@ config SOC_SERIES_BL70X
select CACHE_MANAGEMENT
select CLOCK_CONTROL
select CODE_DATA_RELOCATION
select CPU_HAS_FPU
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select FLOAT_HARD

2
soc/egis/et171/Kconfig
View File

@@ -11,9 +11,9 @@ config SOC_EGIS_ET171
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_F
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
select CPU_HAS_ANDES_EXECIT

2
soc/ite/ec/it8xxx2/Kconfig
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@@ -2,7 +2,7 @@
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_IT8XXX2
select CPU_HAS_FPU if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" || RISCV_ISA_EXT_M
select RISCV_ISA_EXT_F if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" || RISCV_ISA_EXT_M
select HAS_PM
select ARCH_HAS_CUSTOM_CPU_IDLE
select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE

2
soc/qemu/virt_riscv/qemu_virt_riscv32/Kconfig
View File

@@ -2,8 +2,8 @@
# SPDX-License-Identifier: Apache-2.0
config SOC_QEMU_VIRT_RISCV32
select CPU_HAS_FPU
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_F
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select RISCV_HAS_PLIC

3
soc/qemu/virt_riscv/qemu_virt_riscv64/Kconfig
View File

@@ -2,8 +2,9 @@
# SPDX-License-Identifier: Apache-2.0
config SOC_QEMU_VIRT_RISCV64
select CPU_HAS_FPU_DOUBLE_PRECISION
select RISCV_ISA_RV64I
select RISCV_ISA_EXT_F
select RISCV_ISA_EXT_D
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select RISCV_HAS_PLIC

1
soc/sifive/sifive_freedom/fu500/Kconfig
View File

@@ -26,4 +26,3 @@ config SOC_SERIES_SIFIVE_FREEDOM_FU500
config SOC_SIFIVE_FREEDOM_FU540_U54
bool
select RISCV_ISA_EXT_G
select CPU_HAS_FPU_DOUBLE_PRECISION

1
soc/sifive/sifive_freedom/fu700/Kconfig
View File

@@ -25,4 +25,3 @@ config SOC_SERIES_SIFIVE_FREEDOM_FU700
config SOC_SIFIVE_FREEDOM_FU740_U74
bool
select RISCV_ISA_EXT_G
select CPU_HAS_FPU_DOUBLE_PRECISION

2
soc/telink/tlsr/tlsr951x/Kconfig
View File

@@ -8,13 +8,13 @@ config SOC_SERIES_TLSR951X
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_F
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI
select RISCV_PRIVILEGED
select RISCV_HAS_PLIC
select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
select HAS_TELINK_DRIVERS
select CPU_HAS_FPU
select CPU_HAS_DCACHE
select CPU_HAS_ICACHE
select CPU_HAS_ANDES_HWDSP