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drivers: mipi_dsi: Add support Renesas RA MIPI DSI for RA8P1

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Update the Renesas RA MIPI DSI driver and bindings to align
with RA8P1 SoC support:

- Add SoC-specific PHY PLL multiplier ranges
  - RA8D1: 20–180
  - RA8P1: 40–375
- Correct t_init limit from 15 bits to 19 bits as specified in HUM
- Update devicetree bindings:
  - Clarify `pll-div` as input frequency divisor
  - Add `pll-out-div` property as output frequency divisor

Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
This commit is contained in:
Khanh Nguyen
2025-09-15 17:17:23 +07:00
committed by Anas Nashif
parent ea85a8b841
commit 2e7115a45f
2 changed files with 23 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/mipi_dsi/dsi_renesas_ra.c
View File

@@ -224,9 +224,19 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
return 0;
}
#if defined(CONFIG_SOC_SERIES_RA8D1)
#define RENESAS_RA_PHY_PLL_MUL_INT_MIN 20
#define RENESAS_RA_PHY_PLL_MUL_INT_MAX 180
#elif defined(CONFIG_SOC_SERIES_RA8P1)
#define RENESAS_RA_PHY_PLL_MUL_INT_MIN 40
#define RENESAS_RA_PHY_PLL_MUL_INT_MAX 375
#else
#error "Unsupported SoC series"
#endif
#define RENESAS_RA_MIPI_PHYS_SETTING_DEFINE(n) \
static const mipi_phy_timing_t mipi_phy_##n##_timing = { \
.t_init = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_init), 0, 0x7FFF), \
.t_init = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_init), 0, 0x7FFFF), \
.dphytim2_b = \
{ \
.t_clk_prep = \
@@ -266,8 +276,12 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
.pll_settings = \
{ \
.div = DT_INST_PROP(n, pll_div) - 1, \
.pll_div = DT_INST_ENUM_IDX_OR(n, pll_out_div, 0), \
.mul_frac = DT_INST_ENUM_IDX(n, pll_mul_frac), \
.mul_int = CLAMP(DT_INST_PROP(n, pll_mul_int), 20, 180) - 1, \
.mul_int = CLAMP(DT_INST_PROP(n, pll_mul_int), \
RENESAS_RA_PHY_PLL_MUL_INT_MIN, \
RENESAS_RA_PHY_PLL_MUL_INT_MAX) - \
1, \
}, \
.lp_divisor = CLAMP(DT_INST_PROP(n, lp_divisor), 1, 32) - 1, \
.p_timing = &mipi_phy_##n##_timing, \

8
dts/bindings/mipi-dsi/renesas,ra-mipi-dsi.yaml
View File

@@ -23,7 +23,7 @@ properties:
type: int
enum: [1, 2, 3, 4]
description:
PHY PLL divisor.
PHY PLL input frequency divisor.
pll-mul-int:
type: int
@@ -36,6 +36,12 @@ properties:
description:
PHY PLL fractional multiplier.
pll-out-div:
type: int
enum: [1, 2, 4, 8]
description: |
PHY PLL output frequency divisor.
lp-divisor:
type: int
description: