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soc: atmel: Port SAM family to HWMv2

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Port all the Atmel SAM SoCs to HWMv2.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit is contained in:
Gerson Fernando Budke
2024-02-09 21:50:32 +01:00
committed by Carles Cufi
parent da00d0e7b9
commit 3b84b9910a
76 changed files with 1062 additions and 1226 deletions
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3
soc/soc_legacy/arm/atmel_sam/CMakeLists.txt → soc/atmel/sam/CMakeLists.txt
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@@ -1,8 +1,9 @@
# Makefile - Atmel SAM MCU family
#
# Copyright (c) 2016 Piotr Mienkowski
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
#
add_subdirectory(common)
add_subdirectory(${SOC_SERIES})
add_subdirectory_ifdef(CONFIG_ASF common)

12
soc/atmel/sam/Kconfig Normal file
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@@ -0,0 +1,12 @@
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_SAM
select ASF
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
if SOC_FAMILY_SAM
rsource "*/Kconfig"
endif # SOC_FAMILY_SAM

12
soc/soc_legacy/arm/atmel_sam/Kconfig.defconfig → soc/atmel/sam/Kconfig.defconfig
View File

@@ -1,21 +1,25 @@
# Atmel SAM MCU family default configuration options
# Copyright (c) 2016 Piotr Mienkowski
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
source "soc/soc_legacy/arm/atmel_sam/*/Kconfig.defconfig.series"
if SOC_FAMILY_SAM
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
rsource "*/Kconfig.defconfig"
config CLOCK_CONTROL
default y
config GPIO
default y
config PINCTRL
default y
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config WATCHDOG
default y

10
soc/atmel/sam/Kconfig.soc Normal file
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@@ -0,0 +1,10 @@
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_SAM
bool
config SOC_FAMILY
default "atmel_sam" if SOC_FAMILY_SAM
rsource "*/Kconfig.soc"

2
soc/soc_legacy/arm/atmel_sam/common/CMakeLists.txt → soc/atmel/sam/common/CMakeLists.txt
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@@ -1,6 +1,8 @@
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_pmc.c)
zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_gpio.c)
zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_supc.c)

96
soc/atmel/sam/common/Kconfig Normal file
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@@ -0,0 +1,96 @@
# Atmel SAM MCU series general configuration options
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_FAMILY_SAM && !SOC_SERIES_SAM4L
menu "Clocks"
config SOC_ATMEL_SAM_EXT_SLCK
bool "Use external crystal oscillator for slow clock"
help
Says y if you want to use external 32 kHz crystal oscillator to drive
the slow clock. Note that this adds a few seconds to boot time, as the
crystal needs to stabilize after power-up.
Says n if you do not need accurate and precise timers. The slow clock
will be driven by the internal fast RC oscillator running at 32 kHz.
config SOC_ATMEL_SAM_EXT_MAINCK
bool "Use external crystal oscillator for main clock"
default y
help
The main clock is being used to drive the PLL, and thus driving the
processor clock.
Says y if you want to use external crystal oscillator to drive the
main clock. Note that this adds about a second to boot time, as the
crystal needs to stabilize after power-up.
The crystal used here can be from 3 to 20 MHz.
Says n here will use the internal fast RC oscillator running at 12 MHz.
menu "PLL A"
config SOC_ATMEL_SAM_PLLA_MULA
int "PLL MULA"
default 6 if SOC_SERIES_SAM3X
default 9 if SOC_SERIES_SAM4S || SOC_SERIES_SAM4E
default 24 if SOC_SERIES_SAME70 || SOC_SERIES_SAMV71
range 1 62
help
This is the multiplier (MULA) used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings for a particular board.
With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times
the main clock frequency.
config SOC_ATMEL_SAM_PLLA_DIVA
int "PLL DIVA"
default 1
range 1 255
help
This is the divider (DIVA) used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times
the main clock frequency.
config SOC_ATMEL_SAM_MDIV
int "MDIV"
depends on SOC_SERIES_SAME70 || SOC_SERIES_SAMV71
default 2
range 1 4
help
This divisor defines a ratio between processor clock (HCLK)
and master clock (MCK) where the maximum value is 150MHz:
MCK = HCLK / MDIV
endmenu # PLL A
endmenu # clocks
config SOC_ATMEL_SAM_WAIT_MODE
bool "CPU goes to Wait mode instead of Sleep mode"
depends on SOC_ATMEL_SAM_EXT_MAINCK
default y if DEBUG
help
For JTAG debugging CPU clock (HCLK) should not stop. In order to
achieve this, make CPU go to Wait mode instead of Sleep mode while
using external crystal oscillator for main clock.
config SOC_ATMEL_SAM_DISABLE_ERASE_PIN
bool "Disable ERASE pin"
help
At reset ERASE pin is configured in System IO mode. Asserting the
ERASE pin at '1' will completely erase Flash memory. Setting this
option will switch the pin to general IO mode giving control of the
pin to the GPIO module.
endif # SOC_FAMILY_SAM && !SOC_SERIES_SAM4L

0
soc/soc_legacy/arm/atmel_sam/common/atmel_sam_dt.h → soc/atmel/sam/common/atmel_sam_dt.h
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0
soc/soc_legacy/arm/atmel_sam/common/pinctrl_soc.h → soc/atmel/sam/common/pinctrl_soc.h
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0
soc/soc_legacy/arm/atmel_sam/common/pwm_fixup.h → soc/atmel/sam/common/pwm_fixup.h
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0
soc/soc_legacy/arm/atmel_sam/common/soc_gpio.c → soc/atmel/sam/common/soc_gpio.c
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0
soc/soc_legacy/arm/atmel_sam/common/soc_gpio.h → soc/atmel/sam/common/soc_gpio.h
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0
soc/soc_legacy/arm/atmel_sam/common/soc_pmc.c → soc/atmel/sam/common/soc_pmc.c
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0
soc/soc_legacy/arm/atmel_sam/common/soc_pmc.h → soc/atmel/sam/common/soc_pmc.h
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0
soc/soc_legacy/arm/atmel_sam/common/soc_power.c → soc/atmel/sam/common/soc_power.c
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0
soc/soc_legacy/arm/atmel_sam/common/soc_poweroff.c → soc/atmel/sam/common/soc_poweroff.c
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0
soc/soc_legacy/arm/atmel_sam/common/soc_sam4l_gpio.c → soc/atmel/sam/common/soc_sam4l_gpio.c
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0
soc/soc_legacy/arm/atmel_sam/common/soc_sam4l_pm.c → soc/atmel/sam/common/soc_sam4l_pm.c
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0
soc/soc_legacy/arm/atmel_sam/common/soc_sam4l_poweroff.c → soc/atmel/sam/common/soc_sam4l_poweroff.c
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0
soc/soc_legacy/arm/atmel_sam/common/soc_supc.c → soc/atmel/sam/common/soc_supc.c
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0
soc/soc_legacy/arm/atmel_sam/common/soc_supc.h → soc/atmel/sam/common/soc_supc.h
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3
soc/soc_legacy/arm/atmel_sam/sam4l/CMakeLists.txt → soc/atmel/sam/sam3x/CMakeLists.txt
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@@ -1,5 +1,8 @@
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_sources(
soc.c
)

8
soc/soc_legacy/arm/atmel_sam/sam3x/Kconfig.series → soc/atmel/sam/sam3x/Kconfig
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@@ -3,19 +3,13 @@
# Copyright (c) 2014-2015 Wind River Systems, Inc.
# Copyright (c) 2016 Intel Corporation.
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
# Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAM3X
bool "Atmel SAM3X MCU"
select ARM
select CPU_CORTEX_M3
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select SOC_FAMILY_SAM
select PLATFORM_SPECIFIC_INIT
select ASF
select HAS_POWEROFF
help
Enable support for Atmel SAM3X Cortex-M3 microcontrollers.
Part No.: SAM3X8E

14
soc/atmel/sam/sam3x/Kconfig.defconfig Normal file
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@@ -0,0 +1,14 @@
# Atmel SAM3X MCU series configuration options
# Copyright (c) 2014-2015 Wind River Systems, Inc.
# Copyright (c) 2016 Intel Corporation.
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SAM3X
config NUM_IRQS
default 45
endif # SOC_SERIES_SAM3X

43
soc/atmel/sam/sam3x/Kconfig.soc Normal file
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@@ -0,0 +1,43 @@
# Atmel SAM3X MCU series
# Copyright (c) 2014-2015 Wind River Systems, Inc.
# Copyright (c) 2016 Intel Corporation.
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAM3X
bool
select SOC_FAMILY_SAM
help
Enable support for Atmel SAM3X MCU Series
config SOC_SERIES
default "sam3x" if SOC_SERIES_SAM3X
config SOC_SAM3X4C
bool
select SOC_SERIES_SAM3X
config SOC_SAM3X4E
bool
select SOC_SERIES_SAM3X
config SOC_SAM3X8C
bool
select SOC_SERIES_SAM3X
config SOC_SAM3X8E
bool
select SOC_SERIES_SAM3X
config SOC_SAM3X8H
bool
select SOC_SERIES_SAM3X
config SOC
default "sam3x4c" if SOC_SAM3X4C
default "sam3x4e" if SOC_SAM3X4E
default "sam3x8c" if SOC_SAM3X8C
default "sam3x8e" if SOC_SAM3X8E
default "sam3x8h" if SOC_SAM3X8H

14
soc/soc_legacy/arm/atmel_sam/sam3x/soc.c → soc/atmel/sam/sam3x/soc.c
View File

@@ -1,8 +1,8 @@
/*
* Copyright (c) 2013-2015 Wind River Systems, Inc.
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
* Copyright (c) 2023 Basalte bv
* Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -38,11 +38,11 @@ static ALWAYS_INLINE void clock_init(void)
soc_pmc_enable_clock_failure_detector();
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_EXT_SLCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
soc_supc_slow_clock_select_crystal_osc();
}
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
/*
* Setup main external crystal oscillator.
*/
@@ -78,8 +78,8 @@ static ALWAYS_INLINE void clock_init(void)
* With Processor Clock prescaler at 1
* Processor Clock (HCLK) = 84 MHz.
*/
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM3X_PLLA_MULA, 0x3Fu,
CONFIG_SOC_ATMEL_SAM3X_PLLA_DIVA);
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
/*
* Final setup of the Master Clock
@@ -92,14 +92,14 @@ static ALWAYS_INLINE void clock_init(void)
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
/* Disable internal fast RC if we have an external crystal oscillator */
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
soc_pmc_osc_disable_fastrc();
}
}
void z_arm_platform_init(void)
{
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_WAIT_MODE)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
/*
* Instruct CPU to enter Wait mode instead of Sleep mode to
* keep Processor Clock (HCLK) and thus be able to debug

20
soc/soc_legacy/arm/atmel_sam/sam3x/soc.h → soc/atmel/sam/sam3x/soc.h
View File

@@ -1,6 +1,7 @@
/*
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2013-2015 Wind River Systems, Inc.
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,25 +13,24 @@
* drivers for core peripherals as well as symbols specific to Atmel SAM family.
*/
#ifndef _ATMEL_SAM3X_SOC_H_
#define _ATMEL_SAM3X_SOC_H_
#ifndef _SOC_ATMEL_SAM_SAM3X_SOC_H_
#define _SOC_ATMEL_SAM_SAM3X_SOC_H_
#ifndef _ASMLANGUAGE
#define DONT_USE_CMSIS_INIT
#define DONT_USE_PREDEFINED_CORE_HANDLERS
#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
#if defined CONFIG_SOC_PART_NUMBER_SAM3X4C
#if defined(CONFIG_SOC_SAM3X4C)
#include <sam3x4c.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAM3X4E
#elif defined(CONFIG_SOC_SAM3X4E)
#include <sam3x4e.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAM3X8C
#elif defined(CONFIG_SOC_SAM3X8C)
#include <sam3x8c.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAM3X8E
#elif defined(CONFIG_SOC_SAM3X8E)
#include <sam3x8e.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAM3X8H
#elif defined(CONFIG_SOC_SAM3X8H)
#include <sam3x8h.h>
#else
#error Library does not support the specified device.
@@ -49,4 +49,4 @@
#endif /* _ASMLANGUAGE */
#endif /* _ATMEL_SAM3X_SOC_H_ */
#endif /* _SOC_ATMEL_SAM_SAM3X_SOC_H_ */

3
soc/soc_legacy/arm/atmel_sam/sam4e/CMakeLists.txt → soc/atmel/sam/sam4e/CMakeLists.txt
View File

@@ -1,5 +1,8 @@
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_sources(
soc.c
)

8
soc/soc_legacy/arm/atmel_sam/sam4e/Kconfig.series → soc/atmel/sam/sam4e/Kconfig
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@@ -2,20 +2,14 @@
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2018 Vincent van der Locht
# Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAM4E
bool "Atmel SAM4E MCU"
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU
select SOC_FAMILY_SAM
select PLATFORM_SPECIFIC_INIT
select ASF
select HAS_POWEROFF
help
Enable support for Atmel SAM4E Cortex-M4 microcontrollers.
Part No.: SAM4E16E, SAM4E16C, SAM4E8E, SAM4E8C

13
soc/atmel/sam/sam4e/Kconfig.defconfig Normal file
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@@ -0,0 +1,13 @@
# Atmel SAM4E MCU series configuration options
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2018 Vincent van der Locht
# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SAM4E
config NUM_IRQS
default 47
endif # SOC_SERIES_SAM4E

37
soc/atmel/sam/sam4e/Kconfig.soc Normal file
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@@ -0,0 +1,37 @@
# Atmel SAM4E MCU series
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2018 Vincent van der Locht
# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAM4E
bool
select SOC_FAMILY_SAM
help
Enable support for Atmel SAM4E MCU series
config SOC_SERIES
default "sam4e" if SOC_SERIES_SAM4E
config SOC_SAM4E16E
bool
select SOC_SERIES_SAM4E
config SOC_SAM4E16C
bool
select SOC_SERIES_SAM4E
config SOC_SAM4E8E
bool
select SOC_SERIES_SAM4E
config SOC_SAM4E8C
bool
select SOC_SERIES_SAM4E
config SOC
default "sam4e16e" if SOC_SAM4E16E
default "sam4e16c" if SOC_SAM4E16C
default "sam4e8e" if SOC_SAM4E8E
default "sam4e8c" if SOC_SAM4E8C

14
soc/soc_legacy/arm/atmel_sam/sam4e/soc.c → soc/atmel/sam/sam4e/soc.c
View File

@@ -2,7 +2,7 @@
* Copyright (c) 2013-2015 Wind River Systems, Inc.
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2017 Justin Watson
* Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
* Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
* Copyright (c) 2023 Basalte bv
*
* SPDX-License-Identifier: Apache-2.0
@@ -40,11 +40,11 @@ static ALWAYS_INLINE void clock_init(void)
soc_pmc_enable_clock_failure_detector();
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_EXT_SLCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
soc_supc_slow_clock_select_crystal_osc();
}
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
/*
* Setup main external crystal oscillator.
*/
@@ -70,8 +70,8 @@ static ALWAYS_INLINE void clock_init(void)
/*
* Setup PLLA
*/
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM4E_PLLA_MULA, 0x3Fu,
CONFIG_SOC_ATMEL_SAM4E_PLLA_DIVA);
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
/*
* Final setup of the Master Clock
@@ -84,14 +84,14 @@ static ALWAYS_INLINE void clock_init(void)
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
/* Disable internal fast RC if we have an external crystal oscillator */
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
soc_pmc_osc_disable_fastrc();
}
}
void z_arm_platform_init(void)
{
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_WAIT_MODE)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
/*
* Instruct CPU to enter Wait mode instead of Sleep mode to
* keep Processor Clock (HCLK) and thus be able to debug

21
soc/soc_legacy/arm/atmel_sam/sam4e/soc.h → soc/atmel/sam/sam4e/soc.h
View File

@@ -1,9 +1,9 @@
/*
* Copyright (c) 2019-2020 Gerson Fernando Budke <nandojve@gmail.com>
* Copyright (c) 2013-2015 Wind River Systems, Inc.
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2018 Vincent van der Locht
* Copyright (c) 2017 Justin Watson
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2013-2015 Wind River Systems, Inc.
* Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,25 +12,24 @@
* @file SoC configuration macros for the Atmel SAM4E family processors.
*/
#ifndef _ATMEL_SAM4E_SOC_H_
#define _ATMEL_SAM4E_SOC_H_
#ifndef _SOC_ATMEL_SAM_SAM4E_SOC_H_
#define _SOC_ATMEL_SAM_SAM4E_SOC_H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#define DONT_USE_CMSIS_INIT
#define DONT_USE_PREDEFINED_CORE_HANDLERS
#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
#if defined(CONFIG_SOC_PART_NUMBER_SAM4E16E)
#if defined(CONFIG_SOC_SAM4E16E)
#include <sam4e16e.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4E16C)
#elif defined(CONFIG_SOC_SAM4E16C)
#include <sam4e16c.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4E8E)
#elif defined(CONFIG_SOC_SAM4E8E)
#include <sam4e8e.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4E8C)
#elif defined(CONFIG_SOC_SAM4E8C)
#include <sam4e8c.h>
#else
#error Library does not support the specified device.
@@ -49,4 +48,4 @@
#endif /* !_ASMLANGUAGE */
#endif /* _ATMEL_SAM4E_SOC_H_ */
#endif /* _SOC_ATMEL_SAM_SAM4E_SOC_H_ */

3
soc/soc_legacy/arm/atmel_sam/sam3x/CMakeLists.txt → soc/atmel/sam/sam4l/CMakeLists.txt
View File

@@ -1,5 +1,8 @@
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_sources(
soc.c
)

10
soc/atmel/sam/sam4l/Kconfig Normal file
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@@ -0,0 +1,10 @@
# Copyright (c) 2020-2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAM4L
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select PLATFORM_SPECIFIC_INIT
select HAS_POWEROFF

9
soc/atmel/sam/sam4l/Kconfig.defconfig Normal file
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@@ -0,0 +1,9 @@
# Copyright (c) 2020-2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SAM4L
config NUM_IRQS
default 80
endif # SOC_SERIES_SAM4L

107
soc/atmel/sam/sam4l/Kconfig.soc Normal file
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@@ -0,0 +1,107 @@
# Copyright (c) 2020-2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAM4L
bool
select SOC_FAMILY_SAM
help
Enable support for Atmel SAM4L Cortex-M4 microcontrollers.
Part No.: SAM4LS8C, SAM4LS8B, SAM4LS8A, SAM4LS4C, SAM4LS4B,
SAM4LS4A, SAM4LS2C, SAM4LS2B, SAM4LS2A, SAM4LC8C, SAM4LC8B,
SAM4LC8A, SAM4LC4C, SAM4LC4B, SAM4LC4A SAM4LC2C, SAM4LC2B,
SAM4LC2A
config SOC_SERIES
default "sam4l" if SOC_SERIES_SAM4L
config SOC_SAM4LS2A
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LS2B
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LS2C
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LS4A
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LS4B
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LS4C
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LS8A
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LS8B
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LS8C
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LC2A
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LC2B
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LC2C
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LC4A
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LC4B
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LC4C
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LC8A
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LC8B
bool
select SOC_SERIES_SAM4L
config SOC_SAM4LC8C
bool
select SOC_SERIES_SAM4L
config SOC
default "sam4ls2a" if SOC_SAM4LS2A
default "sam4ls2b" if SOC_SAM4LS2B
default "sam4ls2c" if SOC_SAM4LS2C
default "sam4ls4a" if SOC_SAM4LS4A
default "sam4ls4b" if SOC_SAM4LS4B
default "sam4ls4c" if SOC_SAM4LS4C
default "sam4ls8a" if SOC_SAM4LS8A
default "sam4ls8b" if SOC_SAM4LS8B
default "sam4ls8c" if SOC_SAM4LS8C
default "sam4lc2a" if SOC_SAM4LC2A
default "sam4lc2b" if SOC_SAM4LC2B
default "sam4lc2c" if SOC_SAM4LC2C
default "sam4lc4a" if SOC_SAM4LC4A
default "sam4lc4b" if SOC_SAM4LC4B
default "sam4lc4c" if SOC_SAM4LC4C
default "sam4lc8a" if SOC_SAM4LC8A
default "sam4lc8b" if SOC_SAM4LC8B
default "sam4lc8c" if SOC_SAM4LC8C

0
soc/soc_legacy/arm/atmel_sam/sam4l/soc.c → soc/atmel/sam/sam4l/soc.c
View File

44
soc/soc_legacy/arm/atmel_sam/sam4l/soc.h → soc/atmel/sam/sam4l/soc.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
* Copyright (c) 2020-2024 Gerson Fernando Budke <nandojve@gmail.com>
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,8 +7,8 @@
* @file SoC configuration macros for the Atmel SAM4L family processors.
*/
#ifndef _ATMEL_SAM4L_SOC_H_
#define _ATMEL_SAM4L_SOC_H_
#ifndef _SOC_ATMEL_SAM_SAM4L_SOC_H_
#define _SOC_ATMEL_SAM_SAM4L_SOC_H_
#ifndef _ASMLANGUAGE
@@ -16,41 +16,41 @@
#define DONT_USE_PREDEFINED_CORE_HANDLERS
#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
#if defined(CONFIG_SOC_PART_NUMBER_SAM4LS8C)
#if defined(CONFIG_SOC_SAM4LS8C)
#include <sam4ls8c.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS8B)
#elif defined(CONFIG_SOC_SAM4LS8B)
#include <sam4ls8b.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS8A)
#elif defined(CONFIG_SOC_SAM4LS8A)
#include <sam4ls8a.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS4C)
#elif defined(CONFIG_SOC_SAM4LS4C)
#include <sam4ls4c.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS4B)
#elif defined(CONFIG_SOC_SAM4LS4B)
#include <sam4ls4b.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS4A)
#elif defined(CONFIG_SOC_SAM4LS4A)
#include <sam4ls4a.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS2C)
#elif defined(CONFIG_SOC_SAM4LS2C)
#include <sam4ls2c.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS2B)
#elif defined(CONFIG_SOC_SAM4LS2B)
#include <sam4ls2b.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS2A)
#elif defined(CONFIG_SOC_SAM4LS2A)
#include <sam4ls2a.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC8C)
#elif defined(CONFIG_SOC_SAM4LC8C)
#include <sam4lc8c.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC8B)
#elif defined(CONFIG_SOC_SAM4LC8B)
#include <sam4lc8b.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC8A)
#elif defined(CONFIG_SOC_SAM4LC8A)
#include <sam4lc8a.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC4C)
#elif defined(CONFIG_SOC_SAM4LC4C)
#include <sam4lc4c.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC4B)
#elif defined(CONFIG_SOC_SAM4LC4B)
#include <sam4lc4b.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC4A)
#elif defined(CONFIG_SOC_SAM4LC4A)
#include <sam4lc4a.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC2C)
#elif defined(CONFIG_SOC_SAM4LC2C)
#include <sam4lc2c.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC2B)
#elif defined(CONFIG_SOC_SAM4LC2B)
#include <sam4lc2b.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC2A)
#elif defined(CONFIG_SOC_SAM4LC2A)
#include <sam4lc2a.h>
#else
#error Library does not support the specified device.
@@ -220,4 +220,4 @@
#endif /* !_ASMLANGUAGE */
#endif /* _ATMEL_SAM4L_SOC_H_ */
#endif /* _SOC_ATMEL_SAM_SAM4L_SOC_H_ */

3
soc/soc_legacy/arm/atmel_sam/sam4s/CMakeLists.txt → soc/atmel/sam/sam4s/CMakeLists.txt
View File

@@ -1,5 +1,8 @@
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_sources(
soc.c
)

9
soc/soc_legacy/arm/atmel_sam/sam4s/Kconfig.series → soc/atmel/sam/sam4s/Kconfig
View File

@@ -2,20 +2,13 @@
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2018 Vincent van der Locht
# Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
# Copyright (c) 2020-2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAM4S
bool "Atmel SAM4S MCU"
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select SOC_FAMILY_SAM
select PLATFORM_SPECIFIC_INIT
select ASF
select HAS_POWEROFF
help
Enable support for Atmel SAM4S Cortex-M4 microcontrollers.
Part No.: SAM4S16C, SAM4S16B, SAM4S8C, SAM4S8B,
SAM4S4C, SAM4S4B, SAM4S4A, SAM4S2C, SAM4S2B, SAM4S2A

13
soc/atmel/sam/sam4s/Kconfig.defconfig Normal file
View File

@@ -0,0 +1,13 @@
# Atmel SAM4S MCU series configuration options
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2018 Vincent van der Locht
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SAM4S
config NUM_IRQS
default 35
endif # SOC_SERIES_SAM4S

74
soc/atmel/sam/sam4s/Kconfig.soc Normal file
View File

@@ -0,0 +1,74 @@
# Atmel SAM4S MCU series
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2018 Vincent van der Locht
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAM4S
bool
select SOC_FAMILY_SAM
help
Enable support for Atmel SAM4S Cortex-M4 microcontrollers.
Part No.: SAM4S16C, SAM4S16B, SAM4S8C, SAM4S8B,
SAM4S4C, SAM4S4B, SAM4S4A, SAM4S2C, SAM4S2B, SAM4S2A
config SOC_SERIES
default "sam4s" if SOC_SERIES_SAM4S
config SOC_SAM4S2A
bool
select SOC_SERIES_SAM4S
config SOC_SAM4S2B
bool
select SOC_SERIES_SAM4S
config SOC_SAM4S2C
bool
select SOC_SERIES_SAM4S
config SOC_SAM4S4A
bool
select SOC_SERIES_SAM4S
config SOC_SAM4S4B
bool
select SOC_SERIES_SAM4S
config SOC_SAM4S4C
bool
select SOC_SERIES_SAM4S
config SOC_SAM4S8B
bool
select SOC_SERIES_SAM4S
config SOC_SAM4S8C
bool
select SOC_SERIES_SAM4S
config SOC_SAM4S16B
bool
select SOC_SERIES_SAM4S
config SOC_SAM4S16C
bool
select SOC_SERIES_SAM4S
config SOC_SAM4SA16C
bool
select SOC_SERIES_SAM4S
config SOC
default "sam4s2a" if SOC_SAM4S2A
default "sam4s2b" if SOC_SAM4S2B
default "sam4s2c" if SOC_SAM4S2C
default "sam4s4a" if SOC_SAM4S4A
default "sam4s4b" if SOC_SAM4S4B
default "sam4s4c" if SOC_SAM4S4C
default "sam4s8b" if SOC_SAM4S8B
default "sam4s8c" if SOC_SAM4S8C
default "sam4s16b" if SOC_SAM4S16B
default "sam4s16c" if SOC_SAM4S16C
default "sam4sa16c" if SOC_SAM4SA16C

14
soc/soc_legacy/arm/atmel_sam/sam4s/soc.c → soc/atmel/sam/sam4s/soc.c
View File

@@ -2,8 +2,8 @@
* Copyright (c) 2013-2015 Wind River Systems, Inc.
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2017 Justin Watson
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
* Copyright (c) 2023 Basalte bv
* Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -43,11 +43,11 @@ static ALWAYS_INLINE void clock_init(void)
soc_pmc_enable_clock_failure_detector();
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_SLCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
soc_supc_slow_clock_select_crystal_osc();
}
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
/*
* Setup main external crystal oscillator.
*/
@@ -76,8 +76,8 @@ static ALWAYS_INLINE void clock_init(void)
/*
* Setup PLLA
*/
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM4S_PLLA_MULA, 0x3Fu,
CONFIG_SOC_ATMEL_SAM4S_PLLA_DIVA);
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
/*
* Final setup of the Master Clock
@@ -90,14 +90,14 @@ static ALWAYS_INLINE void clock_init(void)
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
/* Disable internal fast RC if we have an external crystal oscillator */
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
soc_pmc_osc_disable_fastrc();
}
}
void z_arm_platform_init(void)
{
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_WAIT_MODE)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
/*
* Instruct CPU to enter Wait mode instead of Sleep mode to
* keep Processor Clock (HCLK) and thus be able to debug

37
soc/soc_legacy/arm/atmel_sam/sam4s/soc.h → soc/atmel/sam/sam4s/soc.h
View File

@@ -1,9 +1,9 @@
/*
* Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
* Copyright (c) 2018 Vincent van der Locht
* Copyright (c) 2017 Justin Watson
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2013-2015 Wind River Systems, Inc.
* Copyright (c) 2016 Intel Corporation.
* Copyright (c) 2017 Justin Watson
* Copyright (c) 2018 Vincent van der Locht
* Copyright (c) 2020-2024 Gerson Fernando Budke <nandojve@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,39 +12,38 @@
* @file SoC configuration macros for the Atmel SAM4S family processors.
*/
#ifndef _ATMEL_SAM4S_SOC_H_
#define _ATMEL_SAM4S_SOC_H_
#ifndef _SOC_ATMEL_SAM_SAM4S_SOC_H_
#define _SOC_ATMEL_SAM_SAM4S_SOC_H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#define DONT_USE_CMSIS_INIT
#define DONT_USE_PREDEFINED_CORE_HANDLERS
#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
#if defined(CONFIG_SOC_PART_NUMBER_SAM4S16C)
#if defined(CONFIG_SOC_SAM4S16C)
#include <sam4s16c.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4SA16C)
#elif defined(CONFIG_SOC_SAM4SA16C)
#include <sam4sa16c.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S16B)
#elif defined(CONFIG_SOC_SAM4S16B)
#include <sam4s16b.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S8C)
#elif defined(CONFIG_SOC_SAM4S8C)
#include <sam4s8c.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S8B)
#elif defined(CONFIG_SOC_SAM4S8B)
#include <sam4s8b.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S4C)
#elif defined(CONFIG_SOC_SAM4S4C)
#include <sam4s4c.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S4B)
#elif defined(CONFIG_SOC_SAM4S4B)
#include <sam4s4b.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S4A)
#elif defined(CONFIG_SOC_SAM4S4A)
#include <sam4s4a.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S2C)
#elif defined(CONFIG_SOC_SAM4S2C)
#include <sam4s2c.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S2B)
#elif defined(CONFIG_SOC_SAM4S2B)
#include <sam4s2b.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S2A)
#elif defined(CONFIG_SOC_SAM4S2A)
#include <sam4s2a.h>
#else
#error Library does not support the specified device.
@@ -63,4 +62,4 @@
#endif /* !_ASMLANGUAGE */
#endif /* _ATMEL_SAM4S_SOC_H_ */
#endif /* _SOC_ATMEL_SAM_SAM4S_SOC_H_ */

3
soc/soc_legacy/arm/atmel_sam/same70/CMakeLists.txt → soc/atmel/sam/same70/CMakeLists.txt
View File

@@ -1,5 +1,8 @@
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_sources(
soc.c
soc_config.c

19
soc/atmel/sam/same70/Kconfig Normal file
View File

@@ -0,0 +1,19 @@
# Atmel SAM E70 MCU series
# Copyright (c) 2016 Piotr Mienkowski
# Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAME70
select ARM
select CPU_CORTEX_M7
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select INIT_ARCH_HW_AT_BOOT
select PLATFORM_SPECIFIC_INIT
select HAS_SWO
select XIP
select HAS_POWEROFF

13
soc/atmel/sam/same70/Kconfig.defconfig Normal file
View File

@@ -0,0 +1,13 @@
# Atmel SAM E70 MCU series configuration options
# Copyright (c) 2016 Piotr Mienkowski
# Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SAME70
config NUM_IRQS
default 74 if SOC_ATMEL_SAME70_REVB
default 71
endif # SOC_SERIES_SAME70

122
soc/atmel/sam/same70/Kconfig.soc Normal file
View File

@@ -0,0 +1,122 @@
# Atmel SAM E70 MCU series
# Copyright (c) 2016 Piotr Mienkowski
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAME70
bool
select SOC_FAMILY_SAM
help
Enable support for Atmel SAM E70 ARM Cortex-M7 Microcontrollers.
Part No.: SAME70J19, SAME70J20, SAME70J21, SAME70N19, SAME70N20,
SAME70N21, SAME70Q19, SAME70Q20, SAME70Q21, SAME70J19B, SAME70J20B,
SAME70J21B, SAME70N19B, SAME70N20B, SAME70N21B, SAME70Q19B,
SAME70Q20B, SAME70Q21B
config SOC_ATMEL_SAME70_REVB
bool
config SOC_SERIES
default "same70" if SOC_SERIES_SAME70
config SOC_SAME70J19
bool
select SOC_SERIES_SAME70
config SOC_SAME70J20
bool
select SOC_SERIES_SAME70
config SOC_SAME70J21
bool
select SOC_SERIES_SAME70
config SOC_SAME70N19
bool
select SOC_SERIES_SAME70
config SOC_SAME70N20
bool
select SOC_SERIES_SAME70
config SOC_SAME70N21
bool
select SOC_SERIES_SAME70
config SOC_SAME70Q19
bool
select SOC_SERIES_SAME70
config SOC_SAME70Q20
bool
select SOC_SERIES_SAME70
config SOC_SAME70Q21
bool
select SOC_SERIES_SAME70
config SOC_SAME70J19B
bool
select SOC_SERIES_SAME70
select SOC_ATMEL_SAME70_REVB
config SOC_SAME70J20B
bool
select SOC_SERIES_SAME70
select SOC_ATMEL_SAME70_REVB
config SOC_SAME70J21B
bool
select SOC_SERIES_SAME70
select SOC_ATMEL_SAME70_REVB
config SOC_SAME70N19B
bool
select SOC_SERIES_SAME70
select SOC_ATMEL_SAME70_REVB
config SOC_SAME70N20B
bool
select SOC_SERIES_SAME70
select SOC_ATMEL_SAME70_REVB
config SOC_SAME70N21B
bool
select SOC_SERIES_SAME70
select SOC_ATMEL_SAME70_REVB
config SOC_SAME70Q19B
bool
select SOC_SERIES_SAME70
select SOC_ATMEL_SAME70_REVB
config SOC_SAME70Q20B
bool
select SOC_SERIES_SAME70
select SOC_ATMEL_SAME70_REVB
config SOC_SAME70Q21B
bool
select SOC_SERIES_SAME70
select SOC_ATMEL_SAME70_REVB
config SOC
default "same70j19" if SOC_SAME70J19
default "same70j20" if SOC_SAME70J20
default "same70j21" if SOC_SAME70J21
default "same70n19" if SOC_SAME70N19
default "same70n20" if SOC_SAME70N20
default "same70n21" if SOC_SAME70N21
default "same70q19" if SOC_SAME70Q19
default "same70q20" if SOC_SAME70Q20
default "same70q21" if SOC_SAME70Q21
default "same70j19b" if SOC_SAME70J19B
default "same70j20b" if SOC_SAME70J20B
default "same70j21b" if SOC_SAME70J21B
default "same70n19b" if SOC_SAME70N19B
default "same70n20b" if SOC_SAME70N20B
default "same70n21b" if SOC_SAME70N21B
default "same70q19b" if SOC_SAME70Q19B
default "same70q20b" if SOC_SAME70Q20B
default "same70q21b" if SOC_SAME70Q21B

16
soc/soc_legacy/arm/atmel_sam/same70/soc.c → soc/atmel/sam/same70/soc.c
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2016 Piotr Mienkowski
* Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
* Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
* SPDX-License-Identifier: Apache-2.0
*/
@@ -43,12 +43,12 @@ static ALWAYS_INLINE void clock_init(void)
soc_pmc_enable_clock_failure_detector();
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_EXT_SLCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
soc_supc_slow_clock_select_crystal_osc();
}
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
/*
* Setup main external crystal oscillator.
*/
@@ -83,8 +83,8 @@ static ALWAYS_INLINE void clock_init(void)
* With Processor Clock prescaler at 1
* Processor Clock (HCLK)=300 MHz.
*/
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAME70_PLLA_MULA, 0x3Fu,
CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA);
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
soc_pmc_enable_upllck(0x3Fu);
@@ -95,19 +95,19 @@ static ALWAYS_INLINE void clock_init(void)
/* Setting PLLA as MCK, first prescaler, then divider and source last */
soc_pmc_mck_set_prescaler(1);
soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAME70_MDIV);
soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAM_MDIV);
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
/* Disable internal fast RC if we have an external crystal oscillator */
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
soc_pmc_osc_disable_fastrc();
}
}
void z_arm_platform_init(void)
{
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_WAIT_MODE)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
/*
* Instruct CPU to enter Wait mode instead of Sleep mode to
* keep Processor Clock (HCLK) and thus be able to debug

46
soc/soc_legacy/arm/atmel_sam/same70/soc.h → soc/atmel/sam/same70/soc.h
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2016 Piotr Mienkowski
* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,53 +11,52 @@
* drivers for core peripherals as well as symbols specific to Atmel SAM family.
*/
#ifndef _ATMEL_SAME70_SOC_H_
#define _ATMEL_SAME70_SOC_H_
#ifndef _SOC_ATMEL_SAM_SAME70_SOC_H_
#define _SOC_ATMEL_SAM_SAME70_SOC_H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#define DONT_USE_CMSIS_INIT
#define DONT_USE_PREDEFINED_CORE_HANDLERS
#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
#if defined CONFIG_SOC_PART_NUMBER_SAME70J19
#if defined(CONFIG_SOC_SAME70J19)
#include <same70j19.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70J20
#elif defined(CONFIG_SOC_SAME70J20)
#include <same70j20.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70J21
#elif defined(CONFIG_SOC_SAME70J21)
#include <same70j21.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70N19
#elif defined(CONFIG_SOC_SAME70N19)
#include <same70n19.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70N20
#elif defined(CONFIG_SOC_SAME70N20)
#include <same70n20.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70N21
#elif defined(CONFIG_SOC_SAME70N21)
#include <same70n21.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q19
#elif defined(CONFIG_SOC_SAME70Q19)
#include <same70q19.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q20
#elif defined(CONFIG_SOC_SAME70Q20)
#include <same70q20.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q21
#elif defined(CONFIG_SOC_SAME70Q21)
#include <same70q21.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70J19B
#elif defined(CONFIG_SOC_SAME70J19B)
#include <same70j19b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70J20B
#elif defined(CONFIG_SOC_SAME70J20B)
#include <same70j20b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70J21B
#elif defined(CONFIG_SOC_SAME70J21B)
#include <same70j21b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70N19B
#elif defined(CONFIG_SOC_SAME70N19B)
#include <same70n19b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70N20B
#elif defined(CONFIG_SOC_SAME70N20B)
#include <same70n20b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70N21B
#elif defined(CONFIG_SOC_SAME70N21B)
#include <same70n21b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q19B
#elif defined(CONFIG_SOC_SAME70Q19B)
#include <same70q19b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q20B
#elif defined(CONFIG_SOC_SAME70Q20B)
#include <same70q20b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q21B
#elif defined(CONFIG_SOC_SAME70Q21B)
#include <same70q21b.h>
#else
#error Library does not support the specified device.
@@ -72,11 +72,11 @@
/** Master Clock (MCK) Frequency */
#define SOC_ATMEL_SAM_MCK_FREQ_HZ \
(SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAME70_MDIV)
(SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAM_MDIV)
/** UTMI PLL clock (UPLLCK) Frequency */
#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480)
#endif /* _ASMLANGUAGE */
#endif /* _ATMEL_SAME70_SOC_H_ */
#endif /* _SOC_ATMEL_SAM_SAME70_SOC_H_ */

49
soc/soc_legacy/arm/atmel_sam/same70/soc_config.c → soc/atmel/sam/same70/soc_config.c
View File

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2016 Piotr Mienkowski
* Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
* SPDX-License-Identifier: Apache-2.0
*/
@@ -22,10 +23,12 @@
*/
static int atmel_same70_config(void)
{
#ifdef CONFIG_SOC_ATMEL_SAME70_DISABLE_ERASE_PIN
/* Disable ERASE function on PB12 pin, this is controlled by Bus Matrix */
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12;
#endif
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_DISABLE_ERASE_PIN)) {
/* Disable ERASE function on PB12 pin, this is controlled
* by Bus Matrix
*/
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12;
}
/* In Cortex-M based SoCs JTAG interface can be used to perform
* IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug
@@ -35,26 +38,26 @@ static int atmel_same70_config(void)
/* Disable TDI function on PB4 pin, this is controlled by Bus Matrix */
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4;
#ifdef CONFIG_LOG_BACKEND_SWO
/* Disable PCK3 clock used by ETM module */
PMC->PMC_SCDR = PMC_SCDR_PCK3;
while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) {
;
if (IS_ENABLED(CONFIG_LOG_BACKEND_SWO)) {
/* Disable PCK3 clock used by ETM module */
PMC->PMC_SCDR = PMC_SCDR_PCK3;
while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) {
;
}
/* Select PLLA clock as PCK3 clock */
PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK;
/* Enable PCK3 clock */
PMC->PMC_SCER = PMC_SCER_PCK3;
/* Wait for PCK3 setup to complete */
while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) {
;
}
/* Enable TDO/TRACESWO function on PB5 pin */
MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5;
} else {
/* Disable TDO/TRACESWO function on PB5 pin */
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5;
}
/* Select PLLA clock as PCK3 clock */
PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK;
/* Enable PCK3 clock */
PMC->PMC_SCER = PMC_SCER_PCK3;
/* Wait for PCK3 setup to complete */
while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) {
;
}
/* Enable TDO/TRACESWO function on PB5 pin */
MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5;
#else
/* Disable TDO/TRACESWO function on PB5 pin */
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5;
#endif
return 0;
}

3
soc/soc_legacy/arm/atmel_sam/samv71/CMakeLists.txt → soc/atmel/sam/samv71/CMakeLists.txt
View File

@@ -1,5 +1,8 @@
# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_sources(
soc.c
soc_config.c

19
soc/atmel/sam/samv71/Kconfig Normal file
View File

@@ -0,0 +1,19 @@
# Atmel SAM V71 MCU series
# Copyright (c) 2016 Piotr Mienkowski
# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAMV71
select ARM
select CPU_CORTEX_M7
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select INIT_ARCH_HW_AT_BOOT
select PLATFORM_SPECIFIC_INIT
select HAS_SWO
select XIP
select HAS_POWEROFF

13
soc/atmel/sam/samv71/Kconfig.defconfig Normal file
View File

@@ -0,0 +1,13 @@
# Atmel SAM V71 MCU series configuration options
# Copyright (c) 2016 Piotr Mienkowski
# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SAMV71
config NUM_IRQS
default 74 if SOC_ATMEL_SAMV71_REVB
default 71
endif # SOC_SERIES_SAMV71

122
soc/atmel/sam/samv71/Kconfig.soc Normal file
View File

@@ -0,0 +1,122 @@
# Atmel SAM V71 MCU series
# Copyright (c) 2016 Piotr Mienkowski
# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAMV71
bool
select SOC_FAMILY_SAM
help
Enable support for Atmel SAM V71 ARM Cortex-M7 Microcontrollers.
Part No.: SAMV71J19, SAMV71J20, SAMV71J21, SAMV71N19, SAMV71N20,
SAMV71N21, SAMV71Q19, SAMV71Q20, SAMV71Q21, SAMV71J19B, SAMV71J20B,
SAMV71J21B, SAMV71N19B, SAMV71N20B, SAMV71N21B, SAMV71Q19B,
SAMV71Q20B, SAMV71Q21B
config SOC_ATMEL_SAMV71_REVB
bool
config SOC_SERIES
default "samv71" if SOC_SERIES_SAMV71
config SOC_SAMV71J19
bool
select SOC_SERIES_SAMV71
config SOC_SAMV71J20
bool
select SOC_SERIES_SAMV71
config SOC_SAMV71J21
bool
select SOC_SERIES_SAMV71
config SOC_SAMV71N19
bool
select SOC_SERIES_SAMV71
config SOC_SAMV71N20
bool
select SOC_SERIES_SAMV71
config SOC_SAMV71N21
bool
select SOC_SERIES_SAMV71
config SOC_SAMV71Q19
bool
select SOC_SERIES_SAMV71
config SOC_SAMV71Q20
bool
select SOC_SERIES_SAMV71
config SOC_SAMV71Q21
bool
select SOC_SERIES_SAMV71
config SOC_SAMV71J19B
bool
select SOC_SERIES_SAMV71
select SOC_ATMEL_SAMV71_REVB
config SOC_SAMV71J20B
bool
select SOC_SERIES_SAMV71
select SOC_ATMEL_SAMV71_REVB
config SOC_SAMV71J21B
bool
select SOC_SERIES_SAMV71
select SOC_ATMEL_SAMV71_REVB
config SOC_SAMV71N19B
bool
select SOC_SERIES_SAMV71
select SOC_ATMEL_SAMV71_REVB
config SOC_SAMV71N20B
bool
select SOC_SERIES_SAMV71
select SOC_ATMEL_SAMV71_REVB
config SOC_SAMV71N21B
bool
select SOC_SERIES_SAMV71
select SOC_ATMEL_SAMV71_REVB
config SOC_SAMV71Q19B
bool
select SOC_SERIES_SAMV71
select SOC_ATMEL_SAMV71_REVB
config SOC_SAMV71Q20B
bool
select SOC_SERIES_SAMV71
select SOC_ATMEL_SAMV71_REVB
config SOC_SAMV71Q21B
bool
select SOC_SERIES_SAMV71
select SOC_ATMEL_SAMV71_REVB
config SOC
default "samv71j19" if SOC_SAMV71J19
default "samv71j20" if SOC_SAMV71J20
default "samv71j21" if SOC_SAMV71J21
default "samv71n19" if SOC_SAMV71N19
default "samv71n20" if SOC_SAMV71N20
default "samv71n21" if SOC_SAMV71N21
default "samv71q19" if SOC_SAMV71Q19
default "samv71q20" if SOC_SAMV71Q20
default "samv71q21" if SOC_SAMV71Q21
default "samv71j19b" if SOC_SAMV71J19B
default "samv71j20b" if SOC_SAMV71J20B
default "samv71j21b" if SOC_SAMV71J21B
default "samv71n19b" if SOC_SAMV71N19B
default "samv71n20b" if SOC_SAMV71N20B
default "samv71n21b" if SOC_SAMV71N21B
default "samv71q19b" if SOC_SAMV71Q19B
default "samv71q20b" if SOC_SAMV71Q20B
default "samv71q21b" if SOC_SAMV71Q21B

14
soc/soc_legacy/arm/atmel_sam/samv71/soc.c → soc/atmel/sam/samv71/soc.c
View File

@@ -41,12 +41,12 @@ static ALWAYS_INLINE void clock_init(void)
soc_pmc_enable_clock_failure_detector();
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAMV71_EXT_SLCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
soc_supc_slow_clock_select_crystal_osc();
}
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
/*
* Setup main external crystal oscillator.
*/
@@ -81,8 +81,8 @@ static ALWAYS_INLINE void clock_init(void)
* With Processor Clock prescaler at 1
* Processor Clock (HCLK)=300 MHz.
*/
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAMV71_PLLA_MULA, 0x3Fu,
CONFIG_SOC_ATMEL_SAMV71_PLLA_DIVA);
soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
soc_pmc_enable_upllck(0x3Fu);
@@ -93,18 +93,18 @@ static ALWAYS_INLINE void clock_init(void)
/* Setting PLLA as MCK, first prescaler, then divider and source last */
soc_pmc_mck_set_prescaler(1);
soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAMV71_MDIV);
soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAM_MDIV);
soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
/* Disable internal fast RC if we have an external crystal oscillator */
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
soc_pmc_osc_disable_fastrc();
}
}
void z_arm_platform_init(void)
{
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAMV71_WAIT_MODE)) {
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
/*
* Instruct CPU to enter Wait mode instead of Sleep mode to
* keep Processor Clock (HCLK) and thus be able to debug

47
soc/soc_legacy/arm/atmel_sam/samv71/soc.h → soc/atmel/sam/samv71/soc.h
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019 Gerson Fernando Budke
* Copyright (c) 2016 Piotr Mienkowski
* Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,53 +11,52 @@
* drivers for core peripherals as well as symbols specific to Atmel SAM family.
*/
#ifndef _ATMEL_SAMV71_SOC_H_
#define _ATMEL_SAMV71_SOC_H_
#ifndef _SOC_ATMEL_SAM_SAMV71_SOC_H_
#define _SOC_ATMEL_SAM_SAMV71_SOC_H_
#include <zephyr/sys/util.h>
#ifndef _ASMLANGUAGE
#define DONT_USE_CMSIS_INIT
#define DONT_USE_PREDEFINED_CORE_HANDLERS
#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
#if defined CONFIG_SOC_PART_NUMBER_SAMV71J19
#if defined(CONFIG_SOC_SAMV71J19)
#include <samv71j19.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J20
#elif defined(CONFIG_SOC_SAMV71J20)
#include <samv71j20.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J21
#elif defined(CONFIG_SOC_SAMV71J21)
#include <samv71j21.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N19
#elif defined(CONFIG_SOC_SAMV71N19)
#include <samv71n19.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N20
#elif defined(CONFIG_SOC_SAMV71N20)
#include <samv71n20.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N21
#elif defined(CONFIG_SOC_SAMV71N21)
#include <samv71n21.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q19
#elif defined(CONFIG_SOC_SAMV71Q19)
#include <samv71q19.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q20
#elif defined(CONFIG_SOC_SAMV71Q20)
#include <samv71q20.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q21
#elif defined(CONFIG_SOC_SAMV71Q21)
#include <samv71q21.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J19B
#elif defined(CONFIG_SOC_SAMV71J19B)
#include <samv71j19b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J20B
#elif defined(CONFIG_SOC_SAMV71J20B)
#include <samv71j20b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J21B
#elif defined(CONFIG_SOC_SAMV71J21B)
#include <samv71j21b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N19B
#elif defined(CONFIG_SOC_SAMV71N19B)
#include <samv71n19b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N20B
#elif defined(CONFIG_SOC_SAMV71N20B)
#include <samv71n20b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N21B
#elif defined(CONFIG_SOC_SAMV71N21B)
#include <samv71n21b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q19B
#elif defined(CONFIG_SOC_SAMV71Q19B)
#include <samv71q19b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q20B
#elif defined(CONFIG_SOC_SAMV71Q20B)
#include <samv71q20b.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q21B
#elif defined(CONFIG_SOC_SAMV71Q21B)
#include <samv71q21b.h>
#else
#error Library does not support the specified device.
@@ -73,7 +72,7 @@
/** Master Clock (MCK) Frequency */
#define SOC_ATMEL_SAM_MCK_FREQ_HZ \
(SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAMV71_MDIV)
(SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAM_MDIV)
/** UTMI PLL clock (UPLLCK) Frequency */
#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480)
@@ -82,4 +81,4 @@
#include "pwm_fixup.h"
#endif /* _ATMEL_SAMV71_SOC_H_ */
#endif /* _SOC_ATMEL_SAM_SAMV71_SOC_H_ */

52
soc/soc_legacy/arm/atmel_sam/samv71/soc_config.c → soc/atmel/sam/samv71/soc_config.c
View File

@@ -1,6 +1,6 @@
/*
* Copyright (c) 2019 Gerson Fernando Budke
* Copyright (c) 2016 Piotr Mienkowski
* Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
* SPDX-License-Identifier: Apache-2.0
*/
@@ -23,12 +23,12 @@
*/
static int atmel_samv71_config(void)
{
#ifdef CONFIG_SOC_ATMEL_SAMV71_DISABLE_ERASE_PIN
/* Disable ERASE function on PB12 pin, this is controlled by Bus
* Matrix
*/
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12;
#endif
if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_DISABLE_ERASE_PIN)) {
/* Disable ERASE function on PB12 pin, this is controlled
* by Bus Matrix
*/
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12;
}
/* In Cortex-M based SoCs JTAG interface can be used to perform
* IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug
@@ -39,26 +39,26 @@ static int atmel_samv71_config(void)
*/
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4;
#ifdef CONFIG_LOG_BACKEND_SWO
/* Disable PCK3 clock used by ETM module */
PMC->PMC_SCDR = PMC_SCDR_PCK3;
while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) {
;
if (IS_ENABLED(CONFIG_LOG_BACKEND_SWO)) {
/* Disable PCK3 clock used by ETM module */
PMC->PMC_SCDR = PMC_SCDR_PCK3;
while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) {
;
}
/* Select PLLA clock as PCK3 clock */
PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK;
/* Enable PCK3 clock */
PMC->PMC_SCER = PMC_SCER_PCK3;
/* Wait for PCK3 setup to complete */
while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) {
;
}
/* Enable TDO/TRACESWO function on PB5 pin */
MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5;
} else {
/* Disable TDO/TRACESWO function on PB5 pin */
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5;
}
/* Select PLLA clock as PCK3 clock */
PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK;
/* Enable PCK3 clock */
PMC->PMC_SCER = PMC_SCER_PCK3;
/* Wait for PCK3 setup to complete */
while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) {
;
}
/* Enable TDO/TRACESWO function on PB5 pin */
MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5;
#else
/* Disable TDO/TRACESWO function on PB5 pin */
MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5;
#endif
return 0;
}

89
soc/atmel/sam/soc.yml Normal file
View File

@@ -0,0 +1,89 @@
family:
- name: atmel_sam
series:
- name: sam3x
socs:
- name: sam3x4c
- name: sam3x4e
- name: sam3x8c
- name: sam3x8e
- name: sam3x8h
- name: sam4e
socs:
- name: sam4e8c
- name: sam4e8e
- name: sam4e16c
- name: sam4e16e
- name: sam4l
socs:
- name: sam4ls2a
- name: sam4ls2b
- name: sam4ls2c
- name: sam4ls4a
- name: sam4ls4b
- name: sam4ls4c
- name: sam4ls8a
- name: sam4ls8b
- name: sam4ls8c
- name: sam4lc2a
- name: sam4lc2b
- name: sam4lc2c
- name: sam4lc4a
- name: sam4lc4b
- name: sam4lc4c
- name: sam4lc8a
- name: sam4lc8b
- name: sam4lc8c
- name: sam4s
socs:
- name: sam4s2a
- name: sam4s2b
- name: sam4s2c
- name: sam4s4a
- name: sam4s4b
- name: sam4s4c
- name: sam4s8b
- name: sam4s8c
- name: sam4s16b
- name: sam4s16c
- name: sam4sa16c
- name: same70
socs:
- name: same70j19
- name: same70j20
- name: same70j21
- name: same70n19
- name: same70n20
- name: same70n21
- name: same70q19
- name: same70q20
- name: same70q21
- name: same70j19b
- name: same70j20b
- name: same70j21b
- name: same70n19b
- name: same70n20b
- name: same70n21b
- name: same70q19b
- name: same70q20b
- name: same70q21b
- name: samv71
socs:
- name: samv71j19
- name: samv71j20
- name: samv71j21
- name: samv71n19
- name: samv71n20
- name: samv71n21
- name: samv71q19
- name: samv71q20
- name: samv71q21
- name: samv71j19b
- name: samv71j20b
- name: samv71j21b
- name: samv71n19b
- name: samv71n20b
- name: samv71n21b
- name: samv71q19b
- name: samv71q20b
- name: samv71q21b

19
soc/soc_legacy/arm/atmel_sam/Kconfig
View File

@@ -1,19 +0,0 @@
# Atmel SAM MCU family configuration options
# Copyright (c) 2016 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
config SOC_FAMILY_SAM
bool
select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
if SOC_FAMILY_SAM
config SOC_FAMILY
string
default "atmel_sam"
# Select SoC Part No. and configuration options
source "soc/soc_legacy/arm/atmel_sam/*/Kconfig.soc"
endif # SOC_FAMILY_SAM

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# Atmel SAM MCU series selection
# Copyright (c) 2016 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
source "soc/soc_legacy/arm/atmel_sam/*/Kconfig.series"

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# Atmel SAM3X MCU series configuration options
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2016 Intel Corporation.
# Copyright (c) 2014-2015 Wind River Systems, Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SAM3X
config SOC_SERIES
default "sam3x"
config SOC_PART_NUMBER
default "sam3x4c" if SOC_PART_NUMBER_SAM3X4C
default "sam3x4e" if SOC_PART_NUMBER_SAM3X4E
default "sam3x8c" if SOC_PART_NUMBER_SAM3X8C
default "sam3x8e" if SOC_PART_NUMBER_SAM3X8E
default "sam3x8h" if SOC_PART_NUMBER_SAM3X8H
#
# SAM3 family has total 45 peripherals capable of
# generating interrupts.
#
config NUM_IRQS
default 45
endif # SOC_SERIES_SAM3X

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# Atmel SAM3X MCU series
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2016 Intel Corporation.
# Copyright (c) 2014-2015 Wind River Systems, Inc.
# SPDX-License-Identifier: Apache-2.0
choice
prompt "Atmel SAM3X MCU Selection"
depends on SOC_SERIES_SAM3X
config SOC_PART_NUMBER_SAM3X4C
bool "SAM3X4C"
config SOC_PART_NUMBER_SAM3X4E
bool "SAM3X4E"
config SOC_PART_NUMBER_SAM3X8C
bool "SAM3X8C"
config SOC_PART_NUMBER_SAM3X8E
bool "SAM3X8E"
config SOC_PART_NUMBER_SAM3X8H
bool "SAM3X8H"
endchoice
if SOC_SERIES_SAM3X
config SOC_ATMEL_SAM3X_EXT_SLCK
bool "Atmel SAM3 to use external crystal oscillator for slow clock"
help
Says y if you want to use external 32 kHz crystal
oscillator to drive the slow clock. Note that this
adds a few seconds to boot time, as the crystal
needs to stabilize after power-up.
Says n if you do not need accurate and precise timers.
The slow clock will be driven by the internal fast
RC oscillator running at 32 kHz.
config SOC_ATMEL_SAM3X_EXT_MAINCK
bool "Atmel SAM3 to use external crystal oscillator for main clock"
help
The main clock is being used to drive the PLL, and
thus driving the processor clock.
Says y if you want to use external crystal oscillator
to drive the main clock. Note that this adds about
a second to boot time, as the crystal needs to
stabilize after power-up.
The crystal used here can be from 3 to 20 MHz.
Says n here will use the internal fast RC oscillator
running at 12 MHz.
config SOC_ATMEL_SAM3X_PLLA_MULA
hex
default 0x06
help
This is the multiplier (MULA) used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
With default of MULA == 6, and DIVA == 1,
PLL is running at 7 times of main clock.
config SOC_ATMEL_SAM3X_PLLA_DIVA
hex
default 0x01
help
This is the divider (DIVA) used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
With default of MULA == 6, and DIVA == 1,
PLL is running at 7 times of main clock.
config SOC_ATMEL_SAM3X_WAIT_MODE
bool "Atmel SAM3 goes to Wait mode instead of Sleep mode"
depends on SOC_ATMEL_SAM3X_EXT_MAINCK
default y if DEBUG
help
For JTAG debugging CPU clock (HCLK) should not stop. In order
to achieve this, make CPU go to Wait mode instead of Sleep
mode while using external crystal oscillator for main clock.
endif # SOC_SERIES_SAM3X

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# Atmel SAM4E MCU series configuration options
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2018 Vincent van der Locht
# Copyright (c) 2019 Gerson Fernando Budke
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SAM4E
config SOC_SERIES
default "sam4e"
config SOC_PART_NUMBER
default "sam4e16e" if SOC_PART_NUMBER_SAM4E16E
default "sam4e16c" if SOC_PART_NUMBER_SAM4E16C
default "sam4e8e" if SOC_PART_NUMBER_SAM4E8E
default "sam4e8c" if SOC_PART_NUMBER_SAM4E8C
#
# SAM4E family has total 47 peripherals capable of
# generating interrupts.
#
config NUM_IRQS
default 47
if NETWORKING
config NET_L2_ETHERNET
default y
endif # NETWORKING
endif # SOC_SERIES_SAM4E

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# Atmel SAM4E MCU series
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2018 Vincent van der Locht
# Copyright (c) 2019 Gerson Fernando Budke
# SPDX-License-Identifier: Apache-2.0
choice
prompt "Atmel SAM4E MCU Selection"
depends on SOC_SERIES_SAM4E
config SOC_PART_NUMBER_SAM4E16E
bool "SAM4E16E"
config SOC_PART_NUMBER_SAM4E16C
bool "SAM4E16C"
config SOC_PART_NUMBER_SAM4E8E
bool "SAM4E8E"
config SOC_PART_NUMBER_SAM4E8C
bool "SAM4E8C"
endchoice
if SOC_SERIES_SAM4E
config SOC_ATMEL_SAM4E_EXT_SLCK
bool "Atmel SAM4E to use external crystal oscillator for slow clock"
help
Says y if you want to use external 32 kHz crystal
oscillator to drive the slow clock. Note that this
adds a few seconds to boot time, as the crystal
needs to stabilize after power-up.
Says n if you do not need accurate and precise timers.
The slow clock will be driven by the internal fast
RC oscillator running at 32 kHz.
config SOC_ATMEL_SAM4E_EXT_MAINCK
bool "Atmel SAM4E to use external crystal oscillator for main clock"
help
The main clock is being used to drive the PLL, and
thus driving the processor clock.
Says y if you want to use external crystal oscillator
to drive the main clock. Note that this adds about
a second to boot time, as the crystal needs to
stabilize after power-up.
The crystal used here can be from 3 to 20 MHz.
Says n here will use the internal fast RC oscillator
running at 12 MHz.
config SOC_ATMEL_SAM4E_PLLA_MULA
hex "PLL MULA"
default 0x09
help
This is the multiplier (MULA) used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
With default of MULA == 9, and DIVA == 1,
PLL is running at 10 times of main clock.
config SOC_ATMEL_SAM4E_PLLA_DIVA
hex "PLL DIVA"
default 0x01
help
This is the divider (DIVA) used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
With default of MULA == 9, and DIVA == 1,
PLL is running at 10 times of main clock.
config SOC_ATMEL_SAM4E_WAIT_MODE
bool "Atmel SAM4E goes to Wait mode instead of Sleep mode"
depends on SOC_ATMEL_SAM4E_EXT_MAINCK
default y if DEBUG
help
For JTAG debugging CPU clock (HCLK) should not stop. In order
to achieve this, make CPU go to Wait mode instead of Sleep
mode while using external crystal oscillator for main clock.
endif # SOC_SERIES_SAM4E

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# Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SAM4L
config SOC_SERIES
default "sam4l"
config SOC_PART_NUMBER
default "sam4ls8c" if SOC_PART_NUMBER_SAM4LS8C
default "sam4ls8b" if SOC_PART_NUMBER_SAM4LS8B
default "sam4ls8a" if SOC_PART_NUMBER_SAM4LS8A
default "sam4ls4c" if SOC_PART_NUMBER_SAM4LS4C
default "sam4ls4b" if SOC_PART_NUMBER_SAM4LS4B
default "sam4ls4a" if SOC_PART_NUMBER_SAM4LS4A
default "sam4ls2c" if SOC_PART_NUMBER_SAM4LS2C
default "sam4ls2b" if SOC_PART_NUMBER_SAM4LS2B
default "sam4ls2a" if SOC_PART_NUMBER_SAM4LS2A
default "sam4lc8c" if SOC_PART_NUMBER_SAM4LC8C
default "sam4lc8b" if SOC_PART_NUMBER_SAM4LC8B
default "sam4lc8a" if SOC_PART_NUMBER_SAM4LC8A
default "sam4lc4c" if SOC_PART_NUMBER_SAM4LC4C
default "sam4lc4b" if SOC_PART_NUMBER_SAM4LC4B
default "sam4lc4a" if SOC_PART_NUMBER_SAM4LC4A
default "sam4lc2c" if SOC_PART_NUMBER_SAM4LC2C
default "sam4lc2b" if SOC_PART_NUMBER_SAM4LC2B
default "sam4lc2a" if SOC_PART_NUMBER_SAM4LC2A
#
# SAM4L family has total 43 peripherals capable of
# generating interrupts.
#
config NUM_IRQS
default 80
# Configure default device drivers. If a feature is supported by more than one
# device driver the default configuration will be placed in the board defconfig
# file.
config USART_SAM
default y
depends on SERIAL
endif # SOC_SERIES_SAM4L

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# Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAM4L
bool "Atmel SAM4L MCU"
select ARM
select CPU_CORTEX_M4
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select SOC_FAMILY_SAM
select PLATFORM_SPECIFIC_INIT
select ASF
select HAS_POWEROFF
help
Enable support for Atmel SAM4L Cortex-M4 microcontrollers.
Part No.: SAM4LS8C, SAM4LS8B, SAM4LS8A, SAM4LS4C, SAM4LS4B,
SAM4LS4A, SAM4LS2C, SAM4LS2B, SAM4LS2A, SAM4LC8C, SAM4LC8B,
SAM4LC8A, SAM4LC4C, SAM4LC4B, SAM4LC4A SAM4LC2C, SAM4LC2B,
SAM4LC2A

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# Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
choice
prompt "Atmel SAM4L MCU Selection"
depends on SOC_SERIES_SAM4L
config SOC_PART_NUMBER_SAM4LS8C
bool "SAM4LS8C"
config SOC_PART_NUMBER_SAM4LS8B
bool "SAM4LS8B"
config SOC_PART_NUMBER_SAM4LS8A
bool "SAM4LS8A"
config SOC_PART_NUMBER_SAM4LS4C
bool "SAM4LS4C"
config SOC_PART_NUMBER_SAM4LS4B
bool "SAM4LS4B"
config SOC_PART_NUMBER_SAM4LS4A
bool "SAM4LS4A"
config SOC_PART_NUMBER_SAM4LS2C
bool "SAM4LS2C"
config SOC_PART_NUMBER_SAM4LS2B
bool "SAM4LS2B"
config SOC_PART_NUMBER_SAM4LS2A
bool "SAM4LS2A"
config SOC_PART_NUMBER_SAM4LC8C
bool "SAM4LC8C"
config SOC_PART_NUMBER_SAM4LC8B
bool "SAM4LC8B"
config SOC_PART_NUMBER_SAM4LC8A
bool "SAM4LC8A"
config SOC_PART_NUMBER_SAM4LC4C
bool "SAM4LC4C"
config SOC_PART_NUMBER_SAM4LC4B
bool "SAM4LC4B"
config SOC_PART_NUMBER_SAM4LC4A
bool "SAM4LC4A"
config SOC_PART_NUMBER_SAM4LC2C
bool "SAM4LC2C"
config SOC_PART_NUMBER_SAM4LC2B
bool "SAM4LC2B"
config SOC_PART_NUMBER_SAM4LC2A
bool "SAM4LC2A"
endchoice

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# Atmel SAM4S MCU series configuration options
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2018 Vincent van der Locht
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SAM4S
config SOC_SERIES
default "sam4s"
config SOC_PART_NUMBER
default "sam4s16c" if SOC_PART_NUMBER_SAM4S16C
default "sam4sa16c" if SOC_PART_NUMBER_SAM4SA16C
default "sam4s16b" if SOC_PART_NUMBER_SAM4S16B
default "sam4s8c" if SOC_PART_NUMBER_SAM4S8C
default "sam4s8b" if SOC_PART_NUMBER_SAM4S8B
default "sam4s4c" if SOC_PART_NUMBER_SAM4S4C
default "sam4s4b" if SOC_PART_NUMBER_SAM4S4B
default "sam4s4a" if SOC_PART_NUMBER_SAM4S4A
default "sam4s2c" if SOC_PART_NUMBER_SAM4S2C
default "sam4s2b" if SOC_PART_NUMBER_SAM4S2B
default "sam4s2a" if SOC_PART_NUMBER_SAM4S2A
#
# SAM4S family has total 35 peripherals capable of
# generating interrupts.
#
config NUM_IRQS
default 35
endif # SOC_SERIES_SAM4S

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# Atmel SAM4S MCU series
# Copyright (c) 2017 Justin Watson
# Copyright (c) 2018 Vincent van der Locht
# SPDX-License-Identifier: Apache-2.0
choice
prompt "Atmel SAM4S MCU Selection"
depends on SOC_SERIES_SAM4S
config SOC_PART_NUMBER_SAM4S16C
bool "SAM4S16C"
config SOC_PART_NUMBER_SAM4SA16C
bool "SAM4SA16C"
config SOC_PART_NUMBER_SAM4S16B
bool "SAM4S16B"
config SOC_PART_NUMBER_SAM4S8C
bool "SAM4S8C"
config SOC_PART_NUMBER_SAM4S8B
bool "SAM4S8B"
config SOC_PART_NUMBER_SAM4S4C
bool "SAM4S4C"
config SOC_PART_NUMBER_SAM4S4B
bool "SAM4S4B"
config SOC_PART_NUMBER_SAM4S4A
bool "SAM4S4A"
config SOC_PART_NUMBER_SAM4S2C
bool "SAM4S2C"
config SOC_PART_NUMBER_SAM4S2B
bool "SAM4S2B"
config SOC_PART_NUMBER_SAM4S2A
bool "SAM4S2A"
endchoice
if SOC_SERIES_SAM4S
config SOC_ATMEL_SAM4S_EXT_SLCK
bool "Atmel SAM4S to use external crystal oscillator for slow clock"
help
Says y if you want to use external 32 kHz crystal
oscillator to drive the slow clock. Note that this
adds a few seconds to boot time, as the crystal
needs to stabilize after power-up.
Says n if you do not need accurate and precise timers.
The slow clock will be driven by the internal fast
RC oscillator running at 32 kHz.
config SOC_ATMEL_SAM4S_EXT_MAINCK
bool "Atmel SAM4S to use external crystal oscillator for main clock"
help
The main clock is being used to drive the PLL, and
thus driving the processor clock.
Says y if you want to use external crystal oscillator
to drive the main clock. Note that this adds about
a second to boot time, as the crystal needs to
stabilize after power-up.
The crystal used here can be from 3 to 20 MHz.
Says n here will use the internal fast RC oscillator
running at 12 MHz.
config SOC_ATMEL_SAM4S_PLLA_MULA
hex "PLL MULA"
default 0x09
help
This is the multiplier (MULA) used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
With default of MULA == 9, and DIVA == 1,
PLL is running at 10 times of main clock.
config SOC_ATMEL_SAM4S_PLLA_DIVA
hex "PLL DIVA"
default 0x01
help
This is the divider (DIVA) used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
With default of MULA == 9, and DIVA == 1,
PLL is running at 10 times of main clock.
config SOC_ATMEL_SAM4S_WAIT_MODE
bool "Atmel SAM4S goes to Wait mode instead of Sleep mode"
depends on SOC_ATMEL_SAM4S_EXT_MAINCK
default y if DEBUG
help
For JTAG debugging CPU clock (HCLK) should not stop. In order
to achieve this, make CPU go to Wait mode instead of Sleep
mode while using external crystal oscillator for main clock.
endif # SOC_SERIES_SAM4S

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# Atmel SAM E70 MCU series configuration options
# Copyright (c) 2016 Piotr Mienkowski
# Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SAME70
config SOC_SERIES
default "same70"
config SOC_PART_NUMBER
default "same70q21" if SOC_PART_NUMBER_SAME70Q21
default "same70q20" if SOC_PART_NUMBER_SAME70Q20
default "same70q19" if SOC_PART_NUMBER_SAME70Q19
default "same70n21" if SOC_PART_NUMBER_SAME70N21
default "same70n20" if SOC_PART_NUMBER_SAME70N20
default "same70n19" if SOC_PART_NUMBER_SAME70N19
default "same70j21" if SOC_PART_NUMBER_SAME70J21
default "same70j20" if SOC_PART_NUMBER_SAME70J20
default "same70j19" if SOC_PART_NUMBER_SAME70J19
default "same70q21b" if SOC_PART_NUMBER_SAME70Q21B
default "same70q20b" if SOC_PART_NUMBER_SAME70Q20B
default "same70q19b" if SOC_PART_NUMBER_SAME70Q19B
default "same70n21b" if SOC_PART_NUMBER_SAME70N21B
default "same70n20b" if SOC_PART_NUMBER_SAME70N20B
default "same70n19b" if SOC_PART_NUMBER_SAME70N19B
default "same70j21b" if SOC_PART_NUMBER_SAME70J21B
default "same70j20b" if SOC_PART_NUMBER_SAME70J20B
default "same70j19b" if SOC_PART_NUMBER_SAME70J19B
#
# SAM E70 family has in total 71 peripherals capable of generating interrupts
# for the revision A and 74 for the revision B (not all Peripheral Identifiers
# are used).
#
config NUM_IRQS
default 74 if SOC_ATMEL_SAME70_REVB
default 71
endif # SOC_SERIES_SAME70

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# Atmel SAM E70 MCU series
# Copyright (c) 2016 Piotr Mienkowski
# Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAME70
bool "Atmel SAME70 MCU"
select ARM
select CPU_CORTEX_M7
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select SOC_FAMILY_SAM
select INIT_ARCH_HW_AT_BOOT
select PLATFORM_SPECIFIC_INIT
select ASF
select HAS_SWO
select XIP
select HAS_POWEROFF
help
Enable support for Atmel SAM E70 ARM Cortex-M7 Microcontrollers.
Part No.: SAME70J19, SAME70J20, SAME70J21, SAME70N19, SAME70N20,
SAME70N21, SAME70Q19, SAME70Q20, SAME70Q21, SAME70J19B, SAME70J20B,
SAME70J21B, SAME70N19B, SAME70N20B, SAME70N21B, SAME70Q19B,
SAME70Q20B, SAME70Q21B

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# Atmel SAM E70 MCU series
# Copyright (c) 2016 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
choice
prompt "Atmel SAME70 MCU Selection"
depends on SOC_SERIES_SAME70
config SOC_PART_NUMBER_SAME70Q21
bool "SAME70Q21"
config SOC_PART_NUMBER_SAME70Q20
bool "SAME70Q20"
config SOC_PART_NUMBER_SAME70Q19
bool "SAME70Q19"
config SOC_PART_NUMBER_SAME70N21
bool "SAME70N21"
config SOC_PART_NUMBER_SAME70N20
bool "SAME70N20"
config SOC_PART_NUMBER_SAME70N19
bool "SAME70N19"
config SOC_PART_NUMBER_SAME70J21
bool "SAME70J21"
config SOC_PART_NUMBER_SAME70J20
bool "SAME70J20"
config SOC_PART_NUMBER_SAME70J19
bool "SAME70J19"
config SOC_PART_NUMBER_SAME70Q21B
bool "SAME70Q21B"
select SOC_ATMEL_SAME70_REVB
config SOC_PART_NUMBER_SAME70Q20B
bool "SAME70Q20B"
select SOC_ATMEL_SAME70_REVB
config SOC_PART_NUMBER_SAME70Q19B
bool "SAME70Q19B"
select SOC_ATMEL_SAME70_REVB
config SOC_PART_NUMBER_SAME70N21B
bool "SAME70N21B"
select SOC_ATMEL_SAME70_REVB
config SOC_PART_NUMBER_SAME70N20B
bool "SAME70N20B"
select SOC_ATMEL_SAME70_REVB
config SOC_PART_NUMBER_SAME70N19B
bool "SAME70N19B"
select SOC_ATMEL_SAME70_REVB
config SOC_PART_NUMBER_SAME70J21B
bool "SAME70J21B"
select SOC_ATMEL_SAME70_REVB
config SOC_PART_NUMBER_SAME70J20B
bool "SAME70J20B"
select SOC_ATMEL_SAME70_REVB
config SOC_PART_NUMBER_SAME70J19B
bool "SAME70J19B"
select SOC_ATMEL_SAME70_REVB
endchoice
if SOC_SERIES_SAME70
config SOC_ATMEL_SAME70_REVB
bool
config SOC_ATMEL_SAME70_EXT_SLCK
bool "Use external crystal oscillator for slow clock"
help
Say y if you want to use external 32 kHz crystal
oscillator to drive the slow clock. Note that this
adds a few seconds to boot time, as the crystal
needs to stabilize after power-up.
Says n if you do not need accurate and precise timers.
The slow clock will be driven by the internal fast
RC oscillator running at 32 kHz.
config SOC_ATMEL_SAME70_EXT_MAINCK
bool "Use external crystal oscillator for main clock"
help
The main clock is being used to drive the PLL, and
thus driving the processor clock.
Say y if you want to use external crystal oscillator
to drive the main clock. Note that this adds about
a second to boot time, as the crystal needs to
stabilize after power-up.
The crystal used here can be from 3 to 20 MHz.
Says n here will use the internal fast RC oscillator
running at 12 MHz.
config SOC_ATMEL_SAME70_MDIV
int "MDIV"
default 2
range 1 4
help
This divisor defines a ratio between processor clock (HCLK)
and master clock (MCK):
MCK = HCLK / MDIV
config SOC_ATMEL_SAME70_PLLA_MULA
int "PLL MULA"
default 24
range 1 62
help
This is the multiplier MULA used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
Setting MULA=0 would disable PLL at boot, this is currently
not supported.
With default of MULA == 24, and DIVA == 1,
PLL is running at 25 times the main clock frequency.
config SOC_ATMEL_SAME70_PLLA_DIVA
int "PLL DIVA"
default 1
range 1 255
help
This is the divider DIVA used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
Setting DIVA=0 would disable PLL at boot, this is currently
not supported.
With default of MULA == 24, and DIVA == 1,
PLL is running at 25 times the main clock frequency.
config SOC_ATMEL_SAME70_WAIT_MODE
bool "Go to Wait mode instead of Sleep mode"
depends on SOC_ATMEL_SAME70_EXT_MAINCK
default y if DEBUG
help
For JTAG debugging CPU clock (HCLK) should not stop. In order
to achieve this, make CPU go to Wait mode instead of Sleep
mode while using external crystal oscillator for main clock.
config SOC_ATMEL_SAME70_DISABLE_ERASE_PIN
bool "Disable ERASE pin"
help
At reset ERASE pin is configured in System IO mode. Asserting the ERASE
pin at '1' will completely erase Flash memory. Setting this option will
switch the pin to general IO mode giving control of the pin to the GPIO
module.
endif # SOC_SERIES_SAME70

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# Atmel SAM V71 MCU series configuration options
# Copyright (c) 2016 Piotr Mienkowski
# Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_SAMV71
config SOC_SERIES
default "samv71"
config SOC_PART_NUMBER
default "samv71q21" if SOC_PART_NUMBER_SAMV71Q21
default "samv71q20" if SOC_PART_NUMBER_SAMV71Q20
default "samv71q19" if SOC_PART_NUMBER_SAMV71Q19
default "samv71n21" if SOC_PART_NUMBER_SAMV71N21
default "samv71n20" if SOC_PART_NUMBER_SAMV71N20
default "samv71n19" if SOC_PART_NUMBER_SAMV71N19
default "samv71j21" if SOC_PART_NUMBER_SAMV71J21
default "samv71j20" if SOC_PART_NUMBER_SAMV71J20
default "samv71j19" if SOC_PART_NUMBER_SAMV71J19
default "samv71q21b" if SOC_PART_NUMBER_SAMV71Q21B
default "samv71q20b" if SOC_PART_NUMBER_SAMV71Q20B
default "samv71q19b" if SOC_PART_NUMBER_SAMV71Q19B
default "samv71n21b" if SOC_PART_NUMBER_SAMV71N21B
default "samv71n20b" if SOC_PART_NUMBER_SAMV71N20B
default "samv71n19b" if SOC_PART_NUMBER_SAMV71N19B
default "samv71j21b" if SOC_PART_NUMBER_SAMV71J21B
default "samv71j20b" if SOC_PART_NUMBER_SAMV71J20B
default "samv71j19b" if SOC_PART_NUMBER_SAMV71J19B
#
# SAM V71 family has in total 71 peripherals capable of generating interrupts
# for the revision A and 74 for the revision B (not all Peripheral Identifiers
# are used).
#
config NUM_IRQS
default 74 if SOC_ATMEL_SAMV71_REVB
default 71
endif # SOC_SERIES_SAMV71

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soc/soc_legacy/arm/atmel_sam/samv71/Kconfig.series
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@@ -1,28 +0,0 @@
# Atmel SAM V71 MCU series
# Copyright (c) 2016 Piotr Mienkowski
# Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_SAMV71
bool "Atmel SAMV71 MCU"
select ARM
select CPU_CORTEX_M7
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_ARM_MPU
select CPU_HAS_FPU_DOUBLE_PRECISION
select CPU_HAS_ICACHE
select CPU_HAS_DCACHE
select SOC_FAMILY_SAM
select INIT_ARCH_HW_AT_BOOT
select PLATFORM_SPECIFIC_INIT
select ASF
select HAS_SWO
select XIP
select HAS_POWEROFF
help
Enable support for Atmel SAM V71 ARM Cortex-M7 Microcontrollers.
Part No.: SAMV71J19, SAMV71J20, SAMV71J21, SAMV71N19, SAMV71N20,
SAMV71N21, SAMV71Q19, SAMV71Q20, SAMV71Q21, SAMV71J19B, SAMV71J20B,
SAMV71J21B, SAMV71N19B, SAMV71N20B, SAMV71N21B, SAMV71Q19B,
SAMV71Q20B, SAMV71Q21B

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# Atmel SAM V71 MCU series
# Copyright (c) 2019 Gerson Fernando Budke
# Copyright (c) 2016 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
choice
prompt "Atmel SAMV71 MCU Selection"
depends on SOC_SERIES_SAMV71
config SOC_PART_NUMBER_SAMV71Q21
bool "SAMV71Q21"
config SOC_PART_NUMBER_SAMV71Q20
bool "SAMV71Q20"
config SOC_PART_NUMBER_SAMV71Q19
bool "SAMV71Q19"
config SOC_PART_NUMBER_SAMV71N21
bool "SAMV71N21"
config SOC_PART_NUMBER_SAMV71N20
bool "SAMV71N20"
config SOC_PART_NUMBER_SAMV71N19
bool "SAMV71N19"
config SOC_PART_NUMBER_SAMV71J21
bool "SAMV71J21"
config SOC_PART_NUMBER_SAMV71J20
bool "SAMV71J20"
config SOC_PART_NUMBER_SAMV71J19
bool "SAMV71J19"
config SOC_PART_NUMBER_SAMV71Q21B
bool "SAMV71Q21B"
select SOC_ATMEL_SAMV71_REVB
config SOC_PART_NUMBER_SAMV71Q20B
bool "SAMV71Q20B"
select SOC_ATMEL_SAMV71_REVB
config SOC_PART_NUMBER_SAMV71Q19B
bool "SAMV71Q19B"
select SOC_ATMEL_SAMV71_REVB
config SOC_PART_NUMBER_SAMV71N21B
bool "SAMV71N21B"
select SOC_ATMEL_SAMV71_REVB
config SOC_PART_NUMBER_SAMV71N20B
bool "SAMV71N20B"
select SOC_ATMEL_SAMV71_REVB
config SOC_PART_NUMBER_SAMV71N19B
bool "SAMV71N19B"
select SOC_ATMEL_SAMV71_REVB
config SOC_PART_NUMBER_SAMV71J21B
bool "SAMV71J21B"
select SOC_ATMEL_SAMV71_REVB
config SOC_PART_NUMBER_SAMV71J20B
bool "SAMV71J20B"
select SOC_ATMEL_SAMV71_REVB
config SOC_PART_NUMBER_SAMV71J19B
bool "SAMV71J19B"
select SOC_ATMEL_SAMV71_REVB
endchoice
if SOC_SERIES_SAMV71
config SOC_ATMEL_SAMV71_REVB
bool
config SOC_ATMEL_SAMV71_EXT_SLCK
bool "Use external crystal oscillator for slow clock"
help
Say y if you want to use external 32 kHz crystal
oscillator to drive the slow clock. Note that this
adds a few seconds to boot time, as the crystal
needs to stabilize after power-up.
Says n if you do not need accurate and precise timers.
The slow clock will be driven by the internal fast
RC oscillator running at 32 kHz.
config SOC_ATMEL_SAMV71_EXT_MAINCK
bool "Use external crystal oscillator for main clock"
help
The main clock is being used to drive the PLL, and
thus driving the processor clock.
Say y if you want to use external crystal oscillator
to drive the main clock. Note that this adds about
a second to boot time, as the crystal needs to
stabilize after power-up.
The crystal used here can be from 3 to 20 MHz.
Says n here will use the internal fast RC oscillator
running at 12 MHz.
config SOC_ATMEL_SAMV71_MDIV
int "MDIV"
default 2
range 1 4
help
This divisor defines a ratio between processor clock (HCLK)
and master clock (MCK):
MCK = HCLK / MDIV
config SOC_ATMEL_SAMV71_PLLA_MULA
int "PLL MULA"
default 24
range 1 62
help
This is the multiplier MULA used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
Setting MULA=0 would disable PLL at boot, this is currently
not supported.
With default of MULA == 24, and DIVA == 1,
PLL is running at 25 times the main clock frequency.
config SOC_ATMEL_SAMV71_PLLA_DIVA
int "PLL DIVA"
default 1
range 1 255
help
This is the divider DIVA used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
Setting DIVA=0 would disable PLL at boot, this is currently
not supported.
With default of MULA == 24, and DIVA == 1,
PLL is running at 25 times the main clock frequency.
config SOC_ATMEL_SAMV71_WAIT_MODE
bool "Go to Wait mode instead of Sleep mode"
depends on SOC_ATMEL_SAMV71_EXT_MAINCK
default y if DEBUG
help
For JTAG debugging CPU clock (HCLK) should not stop. In order
to achieve this, make CPU go to Wait mode instead of Sleep
mode while using external crystal oscillator for main clock.
config SOC_ATMEL_SAMV71_DISABLE_ERASE_PIN
bool "Disable ERASE pin"
help
At reset ERASE pin is configured in System IO mode. Asserting the ERASE
pin at '1' will completely erase Flash memory. Setting this option will
switch the pin to general IO mode giving control of the pin to the GPIO
module.
endif # SOC_SERIES_SAMV71