drivers: interrupt_controller: adapt for mcxe31x series

- adapt for mcxe31x series
- due to some bit defined in header files
  add some conditional macro to separate

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>

drivers/interrupt_controller/Kconfig.nxp_siul2

@@ -15,7 +15,7 @@ if NXP_SIUL2_EIRQ
 config NXP_SIUL2_EIRQ_EXT_INTERRUPTS_MAX
 	int
 	default 8 if SOC_SERIES_S32ZE
-	default 32 if SOC_SERIES_S32K3
+	default 32 if SOC_SERIES_S32K3 || SOC_SERIES_MCXE31X
 	help
 	  Number of SIUL2 external interrupts per controller. This is a SoC
 	  integration option.

drivers/interrupt_controller/intc_nxp_siul2_eirq.c

@@ -28,13 +28,20 @@
 #define SIUL2_IFER0             0x28
 /* SIUL2 Interrupt Filter Maximum Counter Register */
 #define SIUL2_IFMCR(n)          (0x30 + 0x4 * (n))
+#ifndef SIUL2_IFMCR_MAXCNT_MASK
 #define SIUL2_IFMCR_MAXCNT_MASK GENMASK(3, 0)
+#endif
+#ifndef SIUL2_IFMCR_MAXCNT
 #define SIUL2_IFMCR_MAXCNT(v)   FIELD_PREP(SIUL2_IFMCR_MAXCNT_MASK, (v))
+#endif
 /* SIUL2 Interrupt Filter Clock Prescaler Register */
 #define SIUL2_IFCPR             0xb0
+#ifndef SIUL2_IFCPR_IFCP_MASK
 #define SIUL2_IFCPR_IFCP_MASK   GENMASK(3, 0)
+#endif
+#ifndef SIUL2_IFCPR_IFCP
 #define SIUL2_IFCPR_IFCP(v)     FIELD_PREP(SIUL2_IFCPR_IFCP_MASK, (v))
-
+#endif
 /* Handy accessors */
 #define REG_READ(r)     sys_read32(config->base + (r))
 #define REG_WRITE(r, v) sys_write32((v), config->base + (r))