drivers: dma: Introduce BFLB DMA driver
Introduce BFLB's DMA. Signed-off-by: Camille BAUD <mail@massdriver.space>
This commit is contained in:
Camille BAUD
committed by
Benjamin Cabé
Benjamin Cabé
parent
520ea0fa9a
commit
5eb694e68a
@@ -56,3 +56,4 @@ zephyr_library_sources_ifdef(CONFIG_DMA_WCH dma_wch.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_TI_CC23X0 dma_ti_cc23x0.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_NPCX_GDMA dma_npcx_gdma.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_SF32LB dma_sf32lb.c)
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zephyr_library_sources_ifdef(CONFIG_DMA_BFLB dma_bflb.c)
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@@ -103,4 +103,6 @@ source "drivers/dma/Kconfig.npcx"
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source "drivers/dma/Kconfig.sf32lb"
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source "drivers/dma/Kconfig.bflb"
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endif # DMA
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9
drivers/dma/Kconfig.bflb
Normal file
9
drivers/dma/Kconfig.bflb
Normal file
@@ -0,0 +1,9 @@
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# Copyright (c) 2025 MASSDRIVER EI <massdriver.space>
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# SPDX-License-Identifier: Apache-2.0
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config DMA_BFLB
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bool "Bouffalo Lab DMA driver"
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default y
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depends on DT_HAS_BFLB_DMA_ENABLED
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help
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DMA driver for Bouffalo Lab SoCs
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424
drivers/dma/dma_bflb.c
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424
drivers/dma/dma_bflb.c
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@@ -0,0 +1,424 @@
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/*
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* Copyright (c) 2025 MASSDRIVER EI <massdriver.space>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT bflb_dma
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#include <zephyr/device.h>
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#include <soc.h>
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#include <zephyr/drivers/dma.h>
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#include <zephyr/cache.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(dma_bflb, CONFIG_DMA_LOG_LEVEL);
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#include <soc.h>
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#include <bflb_soc.h>
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#include <glb_reg.h>
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#include <common_defines.h>
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#include <bouffalolab/common/dma_reg.h>
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#ifdef CONFIG_SOC_SERIES_BL61X
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#define BFLB_DMA_CLOCK_ADDR (GLB_BASE + GLB_DMA_CFG0_OFFSET)
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#else
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#define BFLB_DMA_CLOCK_ADDR (GLB_BASE + GLB_CLK_CFG2_OFFSET)
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#endif
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#define BFLB_DMA_CH_OFFSET(n) ((n + 1) * 0x100)
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#define BFLB_DMA_CH_NB DT_INST_PROP(0, dma_channels)
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#define BFLB_DMA_WIDTH_BYTE 0
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#define BFLB_DMA_WIDTH_2BYTE 1
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#define BFLB_DMA_WIDTH_WORD 2
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#define BFLB_DMA_WIDTH_2WORD 3
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#define BFLB_DMA_BURST_1 0
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#define BFLB_DMA_BURST_4 1
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#define BFLB_DMA_BURST_8 2
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#define BFLB_DMA_BURST_16 3
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#define BFLB_DMA_FLOW_M_M 0
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#define BFLB_DMA_FLOW_M_P 1
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#define BFLB_DMA_FLOW_P_M 2
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#define BFLB_DMA_FLOW_P_P 3
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#define BFLB_DMA_FLOW_SOFT 0
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#define BFLB_DMA_FLOW_PERI 4
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struct dma_bflb_channel {
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dma_callback_t cb;
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void *user_data;
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};
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struct dma_bflb_data {
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struct dma_bflb_channel channels[BFLB_DMA_CH_NB];
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};
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struct dma_bflb_config {
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uint32_t base_reg;
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};
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static size_t dma_bflb_get_transfer_size(const struct device *dev, uint32_t channel)
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{
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const struct dma_bflb_config *cfg = dev->config;
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uint32_t control;
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size_t size = 1;
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uint32_t width;
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control = sys_read32(cfg->base_reg + DMA_CxCONTROL_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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width = (control & DMA_SWIDTH_MASK) >> DMA_SWIDTH_SHIFT;
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/* Using SOURCE data width */
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switch (width) {
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case BFLB_DMA_WIDTH_BYTE:
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break;
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case BFLB_DMA_WIDTH_2BYTE:
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size *= 2U;
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break;
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case BFLB_DMA_WIDTH_WORD:
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size *= 4U;
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break;
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case BFLB_DMA_WIDTH_2WORD:
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size *= 8U;
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break;
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default:
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return 0;
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}
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return size;
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}
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static void dma_bflb_isr(const struct device *dev)
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{
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const struct dma_bflb_config *cfg = dev->config;
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struct dma_bflb_data *data = dev->data;
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uint32_t status, error;
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status = sys_read32(cfg->base_reg + DMA_INTTCSTATUS_OFFSET);
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error = sys_read32(cfg->base_reg + DMA_INTERRORSTATUS_OFFSET);
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for (uint8_t i = 0; i < BFLB_DMA_CH_NB; i++) {
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if (data->channels[i].cb) {
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if (error & (1 << i)) {
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data->channels[i].cb(dev, data->channels[i].user_data, i, -1);
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} else if (status & (1 << i)) {
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data->channels[i].cb(dev, data->channels[i].user_data, i, 0);
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}
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}
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}
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sys_write32(error, cfg->base_reg + DMA_INTERRCLR_OFFSET);
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sys_write32(status, cfg->base_reg + DMA_INTTCCLEAR_OFFSET);
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}
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static int dma_bflb_configure(const struct device *dev, uint32_t channel,
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struct dma_config *config)
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{
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struct dma_bflb_data *data = dev->data;
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const struct dma_bflb_config *cfg = dev->config;
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struct dma_block_config *block = config->head_block;
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struct dma_bflb_channel *channel_control;
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uint32_t ch_config;
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uint32_t control = 0;
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uint16_t size;
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if (channel >= BFLB_DMA_CH_NB) {
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LOG_ERR("Unsupported channel");
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return -EINVAL;
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}
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if (config->block_count > 1) {
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LOG_ERR("Chained transfers not supported");
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/* TODO: add support for LLI chained transfers. */
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return -ENOTSUP;
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}
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if (block->source_addr_adj == 1 || block->dest_addr_adj == 1) {
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LOG_ERR("Decrement not supported");
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return -EINVAL;
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}
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ch_config = sys_read32(cfg->base_reg
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+ DMA_CxCONFIG_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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ch_config &= ~DMA_LLICOUNTER_MASK;
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ch_config &= ~DMA_FLOWCNTRL_MASK;
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if (config->channel_direction == MEMORY_TO_MEMORY) {
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ch_config |= BFLB_DMA_FLOW_M_M << DMA_FLOWCNTRL_SHIFT;
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} else if (config->channel_direction == PERIPHERAL_TO_MEMORY) {
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ch_config |= BFLB_DMA_FLOW_P_M << DMA_FLOWCNTRL_SHIFT;
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} else if (config->channel_direction == MEMORY_TO_PERIPHERAL) {
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ch_config |= BFLB_DMA_FLOW_M_P << DMA_FLOWCNTRL_SHIFT;
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} else if (config->channel_direction == PERIPHERAL_TO_PERIPHERAL) {
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ch_config |= BFLB_DMA_FLOW_P_P << DMA_FLOWCNTRL_SHIFT;
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} else {
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LOG_ERR("Direction error. %d", config->channel_direction);
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return -EINVAL;
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}
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/* For memory we write here */
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sys_write32(block->source_address, cfg->base_reg + DMA_CxSRCADDR_OFFSET
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+ BFLB_DMA_CH_OFFSET(channel));
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sys_write32(block->dest_address, cfg->base_reg + DMA_CxDSTADDR_OFFSET
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+ BFLB_DMA_CH_OFFSET(channel));
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/* For peripherals we treat the address as the peripheral ID */
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ch_config &= ~DMA_SRCPERIPHERAL_MASK;
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ch_config &= ~DMA_DSTPERIPHERAL_MASK;
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ch_config |= (block->source_address << DMA_SRCPERIPHERAL_SHIFT)
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& DMA_SRCPERIPHERAL_MASK;
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ch_config |= (block->dest_address << DMA_DSTPERIPHERAL_SHIFT)
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& DMA_DSTPERIPHERAL_MASK;
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if (!block->source_addr_adj) {
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control |= DMA_SI;
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}
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if (!block->dest_addr_adj) {
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control |= DMA_DI;
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}
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if (config->source_data_size == 1) {
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control |= BFLB_DMA_WIDTH_BYTE << DMA_SWIDTH_SHIFT;
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} else if (config->source_data_size == 2) {
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control |= BFLB_DMA_WIDTH_2BYTE << DMA_SWIDTH_SHIFT;
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} else if (config->source_data_size == 4) {
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control |= BFLB_DMA_WIDTH_WORD << DMA_SWIDTH_SHIFT;
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} else if (config->source_data_size == 8) {
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control |= BFLB_DMA_WIDTH_2WORD << DMA_SWIDTH_SHIFT;
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} else {
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LOG_ERR("Invalid source data size");
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return -EINVAL;
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}
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if (config->dest_data_size == 1) {
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control |= BFLB_DMA_WIDTH_BYTE << DMA_DWIDTH_SHIFT;
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} else if (config->dest_data_size == 2) {
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control |= BFLB_DMA_WIDTH_2BYTE << DMA_DWIDTH_SHIFT;
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} else if (config->dest_data_size == 4) {
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control |= BFLB_DMA_WIDTH_WORD << DMA_DWIDTH_SHIFT;
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} else if (config->dest_data_size == 8) {
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control |= BFLB_DMA_WIDTH_2WORD << DMA_DWIDTH_SHIFT;
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} else {
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LOG_ERR("Invalid destination data size");
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return -EINVAL;
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}
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if (config->source_burst_length == 1) {
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control |= BFLB_DMA_BURST_1 << DMA_SBSIZE_SHIFT;
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} else if (config->source_burst_length == 4) {
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control |= BFLB_DMA_BURST_4 << DMA_SBSIZE_SHIFT;
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} else if (config->source_burst_length == 8) {
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control |= BFLB_DMA_BURST_8 << DMA_SBSIZE_SHIFT;
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} else if (config->source_burst_length == 16) {
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control |= BFLB_DMA_BURST_16 << DMA_SBSIZE_SHIFT;
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} else {
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LOG_ERR("Invalid source burst size");
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return -EINVAL;
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}
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if (config->dest_burst_length == 1) {
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control |= BFLB_DMA_BURST_1 << DMA_DBSIZE_SHIFT;
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} else if (config->dest_burst_length == 4) {
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control |= BFLB_DMA_BURST_4 << DMA_DBSIZE_SHIFT;
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} else if (config->dest_burst_length == 8) {
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control |= BFLB_DMA_BURST_8 << DMA_DBSIZE_SHIFT;
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} else if (config->dest_burst_length == 16) {
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control |= BFLB_DMA_BURST_16 << DMA_DBSIZE_SHIFT;
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} else {
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LOG_ERR("Invalid destination burst size");
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return -EINVAL;
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}
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size = block->block_size / config->dest_data_size;
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control |= (size << DMA_TRANSFERSIZE_SHIFT) & DMA_TRANSFERSIZE_MASK;
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/* Clear interrupts */
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sys_write32(1U << channel, cfg->base_reg + DMA_INTERRCLR_OFFSET);
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sys_write32(1U << channel, cfg->base_reg + DMA_INTTCCLEAR_OFFSET);
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/* Unmask interrupts */
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ch_config &= ~(DMA_ITC | DMA_IE);
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sys_write32(control, cfg->base_reg
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+ DMA_CxCONTROL_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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sys_write32(ch_config, cfg->base_reg
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+ DMA_CxCONFIG_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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channel_control = &data->channels[channel];
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channel_control->cb = config->dma_callback;
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channel_control->user_data = config->user_data;
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LOG_DBG("Configured channel %d for %08X to %08X (%u)",
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channel,
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block->source_address,
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block->dest_address,
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block->block_size);
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return 0;
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}
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static int dma_bflb_start(const struct device *dev, uint32_t channel)
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{
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const struct dma_bflb_config *cfg = dev->config;
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uint32_t config;
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#ifdef CONFIG_SOC_SERIES_BL61X
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/* on BL61x, we must invalidate the output address to update the memory data */
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uint32_t control = sys_read32(
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cfg->base_reg + DMA_CxCONTROL_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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size_t pending_length = (control & DMA_TRANSFERSIZE_MASK) >> DMA_TRANSFERSIZE_SHIFT;
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uintptr_t addr = sys_read32(
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cfg->base_reg + DMA_CxDSTADDR_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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pending_length *= dma_bflb_get_transfer_size(dev, channel);
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sys_cache_data_flush_and_invd_range((void *)addr, pending_length);
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#endif
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config = sys_read32(cfg->base_reg + DMA_CxCONFIG_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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config |= DMA_E;
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sys_write32(config, cfg->base_reg + DMA_CxCONFIG_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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return 0;
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}
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static int dma_bflb_stop(const struct device *dev, uint32_t channel)
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{
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const struct dma_bflb_config *cfg = dev->config;
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uint32_t config;
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config = sys_read32(cfg->base_reg + DMA_CxCONFIG_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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config &= ~DMA_E;
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sys_write32(config, cfg->base_reg + DMA_CxCONFIG_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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return 0;
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}
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static int dma_bflb_reload(const struct device *dev, uint32_t channel,
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uint32_t src, uint32_t dst, size_t size)
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{
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const struct dma_bflb_config *cfg = dev->config;
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uint32_t control;
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size_t sizediv;
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control = sys_read32(cfg->base_reg + DMA_CxCONTROL_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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sizediv = dma_bflb_get_transfer_size(dev, channel);
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if (!sizediv) {
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return -EINVAL;
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}
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sys_write32(src, cfg->base_reg + DMA_CxSRCADDR_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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sys_write32(dst, cfg->base_reg + DMA_CxDSTADDR_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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size /= sizediv;
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control &= ~DMA_TRANSFERSIZE_MASK;
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control |= (size << DMA_TRANSFERSIZE_SHIFT) & DMA_TRANSFERSIZE_MASK;
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sys_write32(control, cfg->base_reg + DMA_CxCONTROL_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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LOG_DBG("Reloaded channel %d for %08X to %08X (%u)",
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channel, src, dst, size);
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return 0;
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}
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static int dma_bflb_get_status(const struct device *dev, uint32_t channel,
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struct dma_status *stat)
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{
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const struct dma_bflb_config *cfg = dev->config;
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uint32_t config, control, direction;
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if (channel >= BFLB_DMA_CH_NB || stat == NULL) {
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return -EINVAL;
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}
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config = sys_read32(cfg->base_reg + DMA_CxCONFIG_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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control = sys_read32(cfg->base_reg + DMA_CxCONTROL_OFFSET + BFLB_DMA_CH_OFFSET(channel));
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if (config & DMA_E) {
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stat->busy = true;
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} else {
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stat->busy = false;
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}
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stat->pending_length = (control & DMA_TRANSFERSIZE_MASK) >> DMA_TRANSFERSIZE_SHIFT;
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stat->pending_length *= dma_bflb_get_transfer_size(dev, channel);
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if (!stat->pending_length) {
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return -EINVAL;
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}
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direction = ((config & DMA_FLOWCNTRL_MASK) >> DMA_FLOWCNTRL_SHIFT) & BFLB_DMA_FLOW_P_P;
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switch (direction) {
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case BFLB_DMA_FLOW_M_M:
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stat->dir = MEMORY_TO_MEMORY;
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break;
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case BFLB_DMA_FLOW_M_P:
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stat->dir = MEMORY_TO_PERIPHERAL;
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break;
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case BFLB_DMA_FLOW_P_M:
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stat->dir = PERIPHERAL_TO_MEMORY;
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break;
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case BFLB_DMA_FLOW_P_P:
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stat->dir = PERIPHERAL_TO_PERIPHERAL;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int dma_bflb_init(const struct device *dev)
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{
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const struct dma_bflb_config *cfg = dev->config;
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uint32_t tmp;
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/* Ensure DMA clocks are enabled*/
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tmp = sys_read32(BFLB_DMA_CLOCK_ADDR);
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tmp |= 0xFF << GLB_DMA_CLK_EN_POS;
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sys_write32(tmp, BFLB_DMA_CLOCK_ADDR);
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/* Enable DMA controller */
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tmp = sys_read32(cfg->base_reg + DMA_TOP_CONFIG_OFFSET);
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tmp |= DMA_E;
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sys_write32(tmp, cfg->base_reg + DMA_TOP_CONFIG_OFFSET);
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/* Ensure all channels are disabled and their interrupts masked */
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for (int i = 0; i < BFLB_DMA_CH_NB; i++) {
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tmp = sys_read32(cfg->base_reg + DMA_CxCONFIG_OFFSET + BFLB_DMA_CH_OFFSET(i));
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tmp &= ~DMA_E;
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tmp |= DMA_ITC | DMA_IE;
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sys_write32(tmp, cfg->base_reg + DMA_CxCONFIG_OFFSET + BFLB_DMA_CH_OFFSET(i));
|
||||
tmp = sys_read32(cfg->base_reg + DMA_CxCONTROL_OFFSET + BFLB_DMA_CH_OFFSET(i));
|
||||
tmp &= ~DMA_I;
|
||||
sys_write32(tmp, cfg->base_reg + DMA_CxCONTROL_OFFSET + BFLB_DMA_CH_OFFSET(i));
|
||||
}
|
||||
|
||||
/* Ensure all interrupts are cleared */
|
||||
sys_write32(0xFF, cfg->base_reg + DMA_INTERRCLR_OFFSET);
|
||||
sys_write32(0xFF, cfg->base_reg + DMA_INTTCCLEAR_OFFSET);
|
||||
|
||||
IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), dma_bflb_isr,
|
||||
DEVICE_DT_INST_GET(0), 0);
|
||||
irq_enable(DT_INST_IRQN(0));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct dma_bflb_data bflb_dma_data = {0};
|
||||
static struct dma_bflb_config bflb_dma_config = {
|
||||
.base_reg = DT_INST_REG_ADDR(0),
|
||||
};
|
||||
|
||||
static DEVICE_API(dma, dma_bflb_api) = {
|
||||
.config = dma_bflb_configure,
|
||||
.start = dma_bflb_start,
|
||||
.stop = dma_bflb_stop,
|
||||
.reload = dma_bflb_reload,
|
||||
.get_status = dma_bflb_get_status,
|
||||
};
|
||||
|
||||
DEVICE_DT_INST_DEFINE(0, dma_bflb_init, NULL,
|
||||
&bflb_dma_data, &bflb_dma_config, PRE_KERNEL_1,
|
||||
CONFIG_DMA_INIT_PRIORITY, &dma_bflb_api);
|
||||
Reference in New Issue
Block a user