soc: microchip: sam: update MMU for sama7g5 FLEXCOM
When the FLEXCOM is activated in the DT, configure it's register region with strong ordered, read and write access. Signed-off-by: Tony Han <tony.han@microchip.com>
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@@ -9,12 +9,17 @@
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#include <zephyr/arch/arm/mmu/arm_mmu.h>
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#include <zephyr/kernel.h>
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#define MMU_REGION_FLEXCOM_DEFN(idx, n) \
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COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flx##n)), \
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(MMU_REGION_FLAT_ENTRY("flexcom"#n, FLEXCOM##n##_BASE_ADDRESS, 0x4000, \
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),), \
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())
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static const struct arm_mmu_region mmu_regions[] = {
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MMU_REGION_FLAT_ENTRY("vectors", CONFIG_KERNEL_VM_BASE, 0x1000,
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_X),
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MMU_REGION_FLAT_ENTRY("flexcom3", FLEXCOM3_BASE_ADDRESS, 0x4000,
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
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FOR_EACH_IDX(MMU_REGION_FLEXCOM_DEFN, (), 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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MMU_REGION_FLAT_ENTRY("gic", GIC_DISTRIBUTOR_BASE, 0x1100,
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
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